•Condition D: The time VPP may be less than 2.0V and above VSS while turning off isื15ms per occurrence with a total accumulated time in this state ื150ms.
Programming Mode Registers
For application flexibility, various functions, features, and modes are programmable inseven mode registers (MRn) provided by the device as user defined variables that mustbe programmed via a MODE REGISTER SET (MRS) command. Because the default val-ues of the mode registers are not defined, contents of mode registers must be fully ini-tialized and/or re-initialized; that is, they must be written after power-up and/or resetfor proper operation. The contents of the mode registers can be altered by re-executingthe MRS command during normal operation. When programming the mode registers,even if the user chooses to modify only a sub-set of the MRS fields, all address fieldswithin the accessed mode register must be redefined when the MRS command is is-sued. MRS and DLL RESET commands do not affect array contents, which means thesecommands can be executed any time after power-up without affecting the array con-tents.
The MRS command cycle time, tMRD, is required to complete the WRITE operation tothe mode register and is the minimum time required between the two MRS commandsshown in the tMRD Timing figure.
Some of the mode register settings affect address/command/control input functionali-ty. In these cases, the next MRS command can be allowed when the function being up-dated by the current MRS command is completed. These MRS commands don’t applytMRD timing to the next MRS command; however, the input cases have unique MR set-ting procedures, so refer to individual function descriptions:•••••••
Gear-down mode
Per-DRAM addressabilityCMD address latencyCA parity latency modeVREFDQ training valueVREFDQ training modeVREFDQ training range
Some mode register settings may not be supported because they are not required bycertain speed bins.
4Gb: x4, x8, x16 DDR4 SDRAMProgramming Mode Registers
Figure 17: tMRD Timing
T0CK_cCK_tCommandValidValidValidMRS2DESDESDESDESDESMRS2ValidT1T2Ta0Ta1Tb0Tb1Tb2Tc0Tc1Tc2AddressValidValidValidValidValidValidValidValidValidValidValidCKEtMRDSettingsOld settingsUpdating settingsTime BreakDon’t Care
Notes:
1.This timing diagram depicts CA parity mode “disabled” case.
2.tMRD applies to all MRS commands with the following exceptions:
Gear-down mode
CA parity latency modeCMD address latency
Per-DRAM addressability mode
VREFDQ training value, VREFDQ training mode, and VREFDQ training range
The MRS command to nonMRS command delay, tMOD, is required for the DRAM toupdate features, except for those noted in note 2 in figure below where the individualfunction descriptions may specify a different requirement. tMOD is the minimum timerequired from an MRS command to a nonMRS command, excluding DES, as shown inthe tMOD Timing figure.
Figure 18: tMOD Timing
T0CK_cCK_tCommandValidValidValidMRS2DESDESDESDESDESValidValidT1T2Ta0Ta1Ta2Ta3Ta4Tb0Tb1Tb2AddressValidValidValidValidValidValidValidValidValidValidValidCKEtMODUpdating settingsNew settingsSettingsOld settingsTime BreakDon’t Care
Notes:
1.This timing diagram depicts CA parity mode “disabled” case.
2.tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode
VREFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQtraining range
4Gb: x4, x8, x16 DDR4 SDRAMProgramming Mode Registers
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以深圳市美光存储技术有限公司提供的参数为例，以下为MT40A256M16GE-083E IT_B-667H1的详细参数，仅供参考
4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
Mode Register 0
Mode register 0 (MR0) controls various device operating modes as shown in the follow-ing register definition table. Not all settings listed may be available on a die; only set-tings required for speed bin support are available. MR0 is written by issuing the MRScommand while controlling the states of the BGx, BAx, and Ax address pins. The map-ping of address pins during the MRS command is shown in the following MR0 RegisterDefinition table.
Table 6: Address Pin Mapping
AddressBG1BG0BA1BA0A17RASCASWEA13A12A11A10A9bus_n_n_nModeregister
21
20
19
18
17
–
–
–
13
12
11
10
9
A88
A77
A66
A55
A44
A33
A22
A11
A00
Note:1.RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 7: MR0 Register Definition
4Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
Table 7: MR0 Register Definition (Continued)
ModeRegister8DescriptionDLL reset0 = No1 = YesTest mode (TM) – Manufacturer use only0 = Normal operating mode, must be programmed to 0CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out00000 = 9 clocks100001 = 10 clocks00010 = 11 clocks100011 = 12 clocks00100 = 13 clocks100101 = 14 clocks00110 = 15 clocks100111 = 16 clocks01000 = 18 clocks01001 = 20 clocks01010 = 22 clocks01011 = 24 clocks01100 = 23 clocks101101 = 17 clocks101110 = 19 clocks101111 = 21 clocks 110000 = 25 clocks (3DS use only)10001 = 26 clocks10010 = 27 clocks (3DS use only)10011 = 28 clocks10100 = 29 clocks110101 = 30 clocks10110 = 31 clocks110111 = 32 clocksBurst type (BT) – Data burst ordering within a READ or WRITE burst access0 = Nibble sequential1 = InterleaveBurst length (BL) – Data burst size associated with each read or write access00 = BL8 (fixed)01 = BC4 or BL8 (on-the-fly)10 = BC4 (fixed)11 = ReservedNotes:
1.Not allowed when 1/4 rate gear-down mode is enabled.
2.If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28
clocks and RTP should be set to 14 clocks.
712, 6:4, 231:04Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.The ordering of accesses within a burst is determined by the burst length, burst type,and the starting column address as shown in the following table. Burst length optionsinclude fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec-ted coincidentally with the registration of a READ or WRITE command via A12/BC_n.
Table 8: Burst Type and Burst Order
Note 1 applies to the entire tableStartingColumn AddressBurstREAD/(A[2, 1, 0])LengthWRITEBC4READ0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1WRITEBL8READ0, V, V1, V, V0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1WRITENotes:
V, V, VBurst Type = Sequential(Decimal)0, 1, 2, 3, T, T, T, T1, 2, 3, 0, T, T, T, T2, 3, 0, 1, T, T, T, T3, 0, 1, 2, T, T, T, T4, 5, 6, 7, T, T, T, T5, 6, 7, 4, T, T, T, T6, 7, 4, 5, T, T, T, T7, 4, 5, 6, T, T, T, T0, 1, 2, 3, X, X, X, X4, 5, 6, 7, X, X, X, X0, 1, 2, 3, 4, 5, 6, 71, 2, 3, 0, 5, 6, 7, 42, 3, 0, 1, 6, 7, 4, 53, 0, 1, 2, 7, 4, 5, , 5, 6, 7, 0, 1, 2, 35, 6, 7, 4, 1, 2, 3, 06, 7, 4, 5, 2, 3, 0, 17, 4, 5, 6, 3, 0, 1, 20, 1, 2, 3, 4, 5, 6, 7Burst Type = Interleaved(Decimal)0, 1, 2, 3, T, T, T, T1, 0, 3, 2, T, T, T, T2, 3, 0, 1, T, T, T, T3, 2, 1, 0, T, T, T, T4, 5, 6, 7, T, T, T, T5, 4, 7, 6, T, T, T, T6, 7, 4, 5, T, T, T, T7, 6, 5, 4, T, T, T, T0, 1, 2, 3, X, X, X, X4, 5, 6, 7, X, X, X, X0, 1, 2, 3, 4, 5, 6, 71, 0, 3, 2, 5, 4, 7, 62, 3, 0, 1, 6, 7, 4, 53, 2, 1, 0, 7, 6, 5, 44, 5, 6, 7, 0, 1, 2, 35, 4, 7, 6, 1, 0, 3, 26, 7, 4, 5, 2, 3, 0, 17, 6, 5, 4, 3, 2, 1, 00, 1, 2, 3, 4, 5, 6, 7Notes2, 32, 32, 32, 32, 32, 32, 32, 32, 32, 331.0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
2.When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts
two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR andtWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in-ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected duringcolumn time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the startingpoint for tWR and tWTR will not be pulled in by two clocks as described in the BC4(fixed) case.
3.T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.X = “Don’t Care.”
