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专利名称：Input protection circuit for MOS device发明人：Okada, Yoshio c/o Intellectual Property
Division,Imada, Sadao c/o IntellectualProperty Division,Shimizu, Mitsuruc/oIntellectual Property Division
申请号：EP1137.5申请日：190726公开号：EP0352769A3公开日：19910320
专利附图：
摘要：An input protection circuit for MOS devices includes a first resistor (12) and afirst parasitic bipolar transistor (13) connected between an input pad (11) and an inputbuffer circuit (14) of a MOS device. The input protection circuit for MOS devices furtherincludes a second resistor (16) and a second parasitic bipolar transistor (17) connected ata preceding stage of the input buffer circuit (14) so that the gate oxide film of the inputbuffer circuit (14) can be protected from being damaged by static charges or a voltage
which is accidentally generated, without increasing the pattern size of the first parasiticbipolar transistor (13).
申请人：KABUSHIKI KAISHA TOSHIBA,TOSHIBA MICRO-ELECTRONICS CORPORATION
地址：72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 JP,25-1,Ekimaehoncho Kawasaki-ku, Kawasaki-shi JP
国籍：JP,JP
代理机构：Lehn, Werner, Dipl.-Ing.
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