CD74ACT08M96,CD74ACT08M96,CD74ACT08M,CD74ACT08M96,CD74ACT08M96,CD74ACT08M96, 规格书,Datasheet 资料

 CD54ACT08, CD74ACT08QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002DInputs Are TTL-Voltage CompatibleDSpeed of Bipolar F, AS, and S, WithDDDDDSignificantly Reduced Power ConsumptionBalanced Propagation DelaysBuffered Inputs±24-mA Output Drive Current– Fanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process andCircuit DesignExceeds 2-kV ESD Protection PerMIL-STD-883, Method 3015CD54ACT08...F PACKAGECD74ACT08...E OR M PACKAGE(TOP VIEW)1A1B1Y2A2B2YGND1234567141312111098VCC4B4A4Y3B3A3YdescriptionThe ’ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean functionY+A•BorY+A)B in positive logic.ORDERING INFORMATIONTAPACKAGE†PDIP – E–5555°C to 125Cto125°CSOICMSOIC – MCDIP – FTubeTubeTape and reelTubeORDERABLEPART NUMBERCD74ACT08ECD74ACT08MCD74ACT08M96CD54ACT08F3ATOP-SIDEMARKINGCD74ACT08EACT08MCD54ACT08F3A†Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.FUNCTION TABLE(each gate)INPUTSAHLXBHXLOUTPUTYHLLlogic diagram, each gate (positive logic)ABYPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright  2002, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other produts, produtionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1芯天下--http://oneic.com/SCHS312B – JANUARY 2001 – REVISED JUNE 2002CD54ACT08, CD74ACT08QUADRUPLE 2-INPUT POSITIVE-AND GATES absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 VInput clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mAPackage thermal impedance, θJA (see Note 2):E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/WM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/WStorage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditions (see Note 3)TA = 25°CMINVCCVIHVILVIVOIOHIOL∆t/∆vSupply voltageHigh-level input voltageLow-level input voltageInput voltageOutput voltageHigh-level output currentLow-level output currentInput transition rise or fall rate004.520.8VCCVCC–24241000MAX5.5–40°C TO85°CMIN4.520.8VCCVCC–24241000MAX5.5–55°C TO125°CMIN4.520.8VCCVCC–242410MAX5.5VVVVVmAmAns/VUNITNOTE 3:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSIOH = –50 µAIOH = –24 mAIOH = –50 mA‡IOH = –75 mA‡IOL = 50 µAVOLVI = V=VIH or VorVILIOL = 24 mAIOL = 50 mA‡IOL = 75 mA‡IO = 0VCC4.5 V4.5 V5.5 V5.5 V4.5 V4.5 V5.5 V5.5 V5.5 V5.5 V4.5 V to 5.5 V±0.142.4101.65±1402.810±180310µAµAmApF0.10.363.850.10.440.10.51.65VTA = 25°CMIN4.43.94MAX–40°C TO85°CMIN4.43.8MAX–55°C TO125°CMIN4.43.73.85VMAXUNITVOHVI = V=VIH or VorVILIIICC∆ICCCiVI = VCC or GNDVI = VCC or GND,VI = VCC – 2.1 V‡Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimizepower dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/ CD54ACT08, CD74ACT08QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002ACT INPUT LOAD TABLEINPUTA or BUNIT LOAD0.3Unit load is ∆ICC limit specifiedin electrical characteristicstable (e.g., 2.4 mA at 25°C).switching characteristics over recommended operating free-air temperature range,VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)PARAMETERtPLHtPHLFROM(INPUT)AorBA or BTO(OUTPUT)Y–40°C TO85°CMIN3.33.3MAX11.711.7–55°C TO125°CMIN3.23.2MAX12.912.9nsUNIToperating characteristics, VCC = 5 V, TA = 25°CPARAMETERCpdPower dissipation capacitanceTYP50UNITpFPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•3芯天下--http://oneic.com/SCHS312B – JANUARY 2001 – REVISED JUNE 2002CD54ACT08, CD74ACT08QUADRUPLE 2-INPUT POSITIVE-AND GATES PARAMETER MEASUREMENT INFORMATIONS12 × VCCOpenGNDR2 = 500 ΩTESTtPLH/tPHLtPLZ/tPZLtPHZ/tPZHtw3 VLOAD CIRCUITInput1.5 VVOLTAGE WAVEFORMSPULSE DURATION3 V1.5 V0 VtsuDataInput1.5 V10%90%trth90%3 V1.5 V10%0 Vtf1.5 V0 VS1Open2 × VCCGND From OutputUnder TestCL = 50 pF(see Note A)R1 = 500 ΩCLRInput3 V1.5 V0 Vtrec3 VReferenceInputCLK1.5 V0 VVOLTAGE WAVEFORMSRECOVERY TIME3 VVOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMESInput1.5 VtPLH1.5 V0 VtPHL90%tr90%VOH50% VCC10%VOLtf90%trVOHVOLOutputControlOutputWaveform 1S1 at 2 × VCC(see Note B)OutputWaveform 2S1 at GND(see Note B)tPZL3 V1.5 V1.5 V0 VtPLZ≈VCC20% VCCtPZH80% VCC20% VCCVOLtPHZVOH80% VCC≈0 VIn-PhaseOutput50%10%tPHLtPLH50% VCC10%tf50%10%Out-of-PhaseOutput90%VOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESVOLTAGE WAVEFORMSOUTPUT ENABLE AND DISABLE TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.Phase relationships between waveforms are arbitrary.D.For clock inputs, fmax is measured with the input duty cycle at 50%.E.The outputs are measured one at a time with one input transition per measurement.F.tPLH and tPHL are the same as tpd.G.tPZL and tPZH are the same as ten.H.tPLZ and tPHZ are the same as tdis.Figure 1. Load Circuit and Voltage Waveforms4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•芯天下--http://oneic.com/PACKAGEOPTIONADDENDUM

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15-Oct-2009

PACKAGINGINFORMATION

OrderableDeviceCD54ACT08F3ACD74ACT08ECD74ACT08EE4CD74ACT08MCD74ACT08M96CD74ACT08M96E4CD74ACT08M96G4CD74ACT08ME4CD74ACT08MG4

(1)

Status(1)ACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVEACTIVE

PackageTypeCDIPPDIPPDIPSOICSOICSOICSOICSOICSOIC

PackageDrawing

JNNDDDDDD

PinsPackageEcoPlan(2)

Qty141414141414141414

1252550

TBDPb-Free(RoHS)Pb-Free(RoHS)Green(RoHS&noSb/Br)

Lead/BallFinish

A42CUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAUCUNIPDAU

MSLPeakTemp(3)N/AforPkgTypeN/AforPkgTypeN/AforPkgTypeLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIMLevel-1-260C-UNLIM

2500Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)2500Green(RoHS&

noSb/Br)5050

Green(RoHS&noSb/Br)Green(RoHS&noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign.

PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable.OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms\"Lead-Free\"or\"Pb-Free\"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveusedbetweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines\"Green\"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthirdparties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysisonincomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis.

Addendum-Page1

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PACKAGEMATERIALSINFORMATION

www.ti.com

14-Jul-2012

TAPEANDREELINFORMATION

*Alldimensionsarenominal

Device

PackagePackagePinsTypeDrawingSOIC

D

14

SPQ

ReelReelA0DiameterWidth(mm)(mm)W1(mm)330.0

16.4

6.5

B0(mm)9.0

K0(mm)2.1

P1(mm)8.0

WPin1(mm)Quadrant16.0

Q1

CD74ACT08M962500

PackMaterials-Page1

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PACKAGEMATERIALSINFORMATION

www.ti.com

14-Jul-2012

*Alldimensionsarenominal

DeviceCD74ACT08M96

PackageType

SOIC

PackageDrawing

D

Pins14

SPQ2500

Length(mm)

367.0

Width(mm)367.0

Height(mm)

38.0

PackMaterials-Page2

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