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专利名称：Output buffer control circuit of memory
device
发明人：Akira Aono,Mitsuo Isobe申请号：US07/198052申请日：19880524公开号：US04858197A公开日：190815
摘要：In an output buffer control circuit of a memory, the set/reset state of a flip-flopis controlled by an address transition detection output and a read detection outputsupplied when completion of data read from a memory cell is detected, and theactive/inactive state of an output buffer for outputting the readout data from thememory cell is controlled by an output from the flip-flop. According to this arrangement,when an address input transits and the address transition detection output is enabled,the output buffer is inactivated. When data is read out from the memory cell and theread detection output is enabled after the address input transits, the output buffer canbe activated.
申请人：KABUSHIKI KAISHA TOSHIBA
代理机构：Finnegan, Henderson, Farabow, Garrett & Dunner
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