专利内容由知识产权出版社提供
专利名称：PROCESS FOR IMPROVING CAPACITANCE
EXTRACTION PERFORMANCE
发明人：Robert J. Allen,Susan E. Cellier,Lewis W.
Dewey, III,Anthony D. Hagin,Adam P.Matheny,Ronald D. Rose,David J. Widiger
申请号：US15832249申请日：20171205
公开号：US20180082009A1公开日：20180322
专利附图：
摘要：Disclosed is a method for improving capacitance extraction performance in a
circuit, the method including mapping, via a computing resource, a first layout including aplurality of wiring paths, selecting at least one target wire from the plurality of wiringpaths, selecting at least one group of wires running orthogonally to the at least onetarget wire, identifying and selecting within the at least one group at least one set of twoor more wires that are combinable for representation as a single merged wire, mapping asecond layout, via the computing resource, and representing the at least one set of twoor more wires as the single merged wire in said second layout, analyzing parasiticcapacitance between the at least one target wire and the at least one group of wiresusing the second layout, and manufacturing the circuit using information from theanalyzing of parasitic capacitance.
申请人：International Business Machines Corporation
地址：Armonk NY US
国籍：US
更多信息请下载全文后查看
