AT90SP0801资料

Features

••••••••

Secure Computation of Public Key Signatures

Secure Storage and Decryption of Symmetric Keys On-chip Cache for Frequently Used Keys SMBus Communications Port

On-board Public Key Computation Engine and Microprocessor Physical and Logical Security Measures to Inhibit Attacks 20-lead SOIC Package, 0°C to +70°C Operating Range3.3V ±10% Supply Voltage

Description

The AT90SP0801 is used to perform cryptographic operations, using asymmetric pri-vate keys stored in its internal EEPROM. An arbitrary number of private keys can bestored externally and decrypted by the chip when required. Communication to the sys-tem processor is via the SMBus.Figure 1. Pin Configuration

Secure Signature Generation ChipAT90SP0801SummaryNameRESETSCLSDAGNDCLKINVCCTEST

Description

Reset Input, Active-lowSMBus ClockSMBus DataGroundInput ClockOperating VoltageDo Not Connect

28-lead TSSOPRESETNCNCNCNCNCSCLSDANCNCNCGNDNCNC123456710111213142827262524232221201918171615NCNCVCCNCNCNCNCNCCLKINTESTTESTNCNCNC28-lead SOICRESETNCNCNCNCSCLSDANCNCGND12345671020191817161514131211VCCNCNCNCNCCLKINTESTNCNCTESTRev. 1495AS–01/02Note: This is a summary document. A complete document isavailable under NDA. For more information, please contact yourlocal Atmel sales office.

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Figure 2. Block Diagram

EEPROMRegistersHardware Key Private Key PasswordUser Key Buffer 0 Private Key Password, Mode CRC TagUser Key Buffer 1 Private Key Password, Mode CRC TagDataI/O BufferSMBus8/16-bitCrypto DataBufferCommandsAVRµpCLKINRESETProgramMemoryPublic KeyCryptoEngineKey:Control:Data:Other ConfigurationRegisters: LOCK, STATUS ERROR, VERS FAILCNT, CONFIG2

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AT90SP0801

Serial Interface

Data is transferred to or from the I/O buffer on the chip using the SMBus interface, in amanner similar but not identical to that of standard two-wire serial EEPROMs.

All bits are sent to or read from the chip most significant bit first, in a manner consistentwith standard serial EEPROMs. Bit fields listed in this document are correspondinglylisted with the MSB on the left and the LSB on the right. Hex numbers are specified withthe “0x” prefix.

Multi-byte information sent to the chip is sent most significant byte first, following typicalconventions. Within the chip, the first byte sent to the chip is stored in memory at thelowest address, and the address is incremented for subsequent bytes. When a mes-sage digest (hash) is sent to the chip, the first byte of the hash value is the first byte tobe sent to the chip.

In both the text and graphics, the chip is the slave and the system is the master. The fol-lowing abbreviations apply:

ANSP

Acknowledge (bus pulled low, master or slave)Not Acknowledge (bus left high, master or slave)Start (High-to-low on SDA with SCL high, master)Stop (Low-to-high on SDA with SCL high, master)

For the graphical representations, the direction of the data flow is indicated as below:

Slave to Master (Chip to System)

Master to Slave (System to Chip)

SMBus Standard Usage

Data transfer to and from the chip follows the SMBus V1.1 standard, using only some ofthe command protocols.

The “write” command of this chip uses the “Block Write” protocol of the SMBus spec.Note that in this chip the count value can exceed 32. This chip does not support the“Write Byte” and “Write Word” protocols of the SMBus spec.

The “Read” command of this chip uses the “Block Read” protocol of the SMBus spec.Note that in this chip the “Read” command can be optionally executed without the pre-ceding partial block write command. This chip does not support the “Receive Byte”,“Read Byte” and “Read Word” protocols of the SMBus spec.

All other commands of this chip use the “Send Byte” protocol of the SMBus spec. Notethat the “Quick Command” and “Process Call” protocols of the SMBus spec are not sup-ported by this chip.

Two-wire Serial EEPROM Comparison

Some of the differences between this chip and a standard two-wire serial EEPROM are:1.The slave address of this chip is different from the A0-AF (hex) standard for

EEPROMs.2.The maximum clock rate is 100 kHz and Tdh is 300 ns. These specs are part of

SMbus.3.The supply voltage is 3.0V to 3.7V.

4.The read address is not specified in the aborted read command.

5.Multi-byte reads and writes are preceded by the number of bytes that will be

transferred.

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6.Multi-byte writes longer than the maximum size of the register (i.e., containing

more bytes) cause an error.

Commands Without Data Transfer

There are a number of commands (described within the following Commands sections)that perform various internal operations on the chip, using data already stored in eitherthe I/O buffer or the internal memories of the chip. All such commands are composed oftwo bytes sent to the chip according to the following flow:

P

Number of bits1

S

7

Slave Address

1

Wr

1

A

8

Command Code

1

A

1

Start Condition

R/W BitAcknowledge

Stop Condition

Write Commands

The write commands permit data to be transferred to the I/O buffer located within theSRAM on the chip. Only block writes are supported, so transfers of 1 or 2 bytes require the same basic sequence as 32 bytes.The commands are encoded as follows:

Slave Address010100000101001001010000

s

Command Code

1

DescriptionWritebuffer,(+data)Writecommand,ignoredWritecommand,ignored

s

0

000000

0111111101111111

The following figure shows the structure for block write operations:

1S

7Slave Address

1Wr

1A

8

Command Code

1A

...

8

Byte Count = N

1A

8Data byte 1

1A

8Data byte 2

1A

...

8Data byte N

1A

1P

The write buffer command is followed by up to 255 bytes of data. All bytes are sourcedby the host and are formatted as follows:

01010000

s1s0000000

count

data0

data1

…

dataN

crc0

crc1

Count denotes the total number of bytes that follows the command, including any CRCbytes. A 0 value is illegal. 255 is the max. number of bytes that may be written percommand.

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AT90SP0801

Data is sent least significant byte first. In some circumstances, there may be no data,only crc.

Depending on the value of ss, the crc bytes may or may not be included.

The two sequence bits s1-0 within the command code tell the chip how to relate thistransfer to previous and subsequent transfers.

S0 if set to a 1 indicates that this is the first transfer to the buffer and that data0 shouldgo into buffer address 0 and so on. If this bit is set to a 0, then data0 will be stored in thenext location within the buffer after that from the previous transfer. When set, this bitalso resets the CRC generator.

S1 if set to a 1 indicates that this is the last transfer to the buffer. If set to a 0, the chipmust have previously executed a command where s0 was set to a 1. When s1 is set to a1, the last two bytes of the information transferred in this block are a CRC value. Thechip will NACK the crc1 byte, if the value sent does not match that computed on theincoming data. The CRC bytes may not be split across two blocks.

For instance, to write password information ( bytes) to the chip, the followingsequence of three write commands would be used (assuming 32 byte loads). TheACKs, NACKs and STOP conditions have been ignored for clarity.

SSS

010100000101000001010000

010000000000000010000000

001000000010000000000010

data0data32crc0

data1data33crc1

data2data34

......

data31data63

For shorter data transfer values, it is perfectly legal for both s0 and s1 to be set. This indi-cates that the entire transfer is taking place in a single block access. As an example ofthis, the following command would write a single byte to the buffer:

S

01010000

11000000

00000011

data0

crc0

crc1

The chip will NACK writes that attempt to write into the chip beyond the internal buffer,which may be as short as 320 bytes.

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Read Commands

Slave Address0101001101010001

Block read commands are slightly different than writes and are encoded as follows:

Command Code----------------DescriptionReadbuffer,firstblockRead,subsequentblk

The read command is only one byte long, and the chip (not the host) sends back thecount information. The count value will always be the smaller of MAXBLK_R or the(remaining) number of bytes in the register that have not been read yet.

When there are a large number of bytes in the buffer, multiple read commands must beexecuted to read all the bytes out of the chip. Using the slave address of 0x53 will causethe chip to start reading at the beginning of the buffer. Using the slave address of 0x51will cause the chip to continue reading information that is subsequent to the informationlast read by the chip from the buffer. After a load or crypto operation, the first commandmay also be a 0x51, which will have the same effect as 0x53.Block Reads are formatted as follows:

1S

7Slave Address

1Rd

1A

8

Byte Count = N

1A

...

8Data Byte 1

1A

8Data Byte 2

1A

...

Data Byte N

8

1N

1P

After the last byte has been read from the register, the read pointer is reset back to thebeginning of the register, and the system may continue to read from the beginning of thebuffer again, if desired. There is no indication from the chip as to when the read pointerhas been reset (other than as may be inferred from the values in the count field).To be compatible with the SMBus specification, the read command may optionally bepreceded by the first two bytes of either of the “ignored write” commands, which are thenaborted with a new start bit for the read. The two bytes of the write command are com-pletely ignored by the chip in this case, and a different encoding for the second byte(01111111, or 0x7F) must be used. Execution of a block read sequence using a legalwrite command code for the second byte (00, 0x40, 0x80 or 0xC) is undefined. The protocol for this is shown below:

1S

7Slave Address

1Wr

1A

80111 1111

1A

1S

7Slave Address

1Rd

1A

...

8

Byte Count = N

1A

8Data byte 1

1A

8Data byte 2

1A

...

8Data byte N

1N

1P

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AT90SP0801

As an example of the read block command, the following would take place to read fourbytes of data from the buffer (assuming that the load VERS_R command had previouslybeen executed).

S

01010011

00000100

data0

data1

data2

data3

or

S

01010010

01111111

S

01010011

00000100

data0

data1

data2

data3

As an example of multiple read block command, the following would take place to readthe 1040 bits (130 bytes) of signature data from the buffer (assuming that the “sign”command had previously been executed). As earlier, the two-byte aborted write is anoption on each command. Note that the first byte read (data0) is the most significantbyte of the signature, while data128 is the most significant byte of the CRC.

SSSSS

0101001001010000010100000101000001010000

0111111101111111011111110111111101111111

SSSSS

0101001101010001010100010101000101010001

0010000000100000001000000010000000000010

data0data32datadata96data128

data1data33data65data97data129

...............

data31data63data95data127

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Absolute Maximum Ratings

Operating Temperature...................................0°C to +70°CStorage Temperature (without bias)................0°C to +70°CVotage on I/O Pins..................................-0.1 to VCC +0.3VVoltage on VCC with Respect to Ground......................6.0VMaximum ESD Voltage..............................................2000V

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification may cause temporary or permanent failure. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Serial Interface AC SpecificationsNametSCLtLOWtHIGHtItAAtBUFtHD.STAtSU.STAtHD.DATtSU.DATtRtFtSU.STOtDHtWRtCLKINtCLKO, tCKH1

69344.7300

1010050

0.14.74.04.70200

1.0300

4.74.0

1004.5

Min

Max100

CL = 1 TTL Gate and 100 pF, except as noted. VCC = 3.0V to 3.7V.

UnitskHzµsµsnsµsµsµsµsµsnsµsnsµsnsmsnsns

Notes

Clock (SCL) FrequencyClock (SCL) Pulse Low-widthClock (SCL) Pulse High-widthNoise Suppression, Not TestedClock low to Data out valid

Bus free before Transmission, Not TestedStart Hold TimeStart Set-up TimeData In Hold TimeData In Set-up TimeInputs Rise Time, Not TestedInputs Fall time, Not TestedStop Set-up TimeData Out Hold Time

Write Cycle Time, EEPROM WriteCLKIN Period

CLKIN Low or CLKIN High

Figure 3. Timing Diagram for Serial Interface AC Specification

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AT90SP0801

Serial Interface DC Specifications

Operating Temperature Range = 0° to 70°C.

NameVCCICC(1)ISB(1)ILIOVILVIHVOLCIOfCLKINNotes:

1

14.318

15

−0.1VCC x 0.7Min3.0

18500.1Typ

Max3.7251003.0VCC x 0.3VCC0.4

UnitsVmAµAµAVVVpFMHz

IOL = 2.1 mA

SCL, SDA, Not TestedDuty cycle >48% and <52%Notes

Operating Voltage, VCC PinAt VCC = 3.7V, fSDA = 100 kHzAt VCC = 3.3V, CLKIN = VSS SDA, SCL. VIN = VCC or VSS

1.The specifications noted as “not tested” denote parameters that are characterized and not 100% tested.2.Preliminary data, subject to change.

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Ordering Information

Ordering CodeAT90SP0801-01SC

Package

20S, 20-lead SOIC

Operation RangeCommercial(0°C to 70°C)

Package Type

20S

20-lead, 0.300 Wide, Plastic Gull Wing Small Outline (SOIC)

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Packaging Information

20S, 20 Lead, 0.300\" Wide, Plastic Gull Wing Small Outline (SOIC)Dimensions in Inches and (Millimeters)28A, 28-lead, 6.1mm Wide, Thin Shrink Small Outline Package (TSSOP)Dimensions in Inches and (Millimeters)0.020 (0.508)0.013 (0.330).0075\" (0.19).0118\" (0.30)PIN 10.299 (7.60)0.420 (10.7)0.291 (7.39)0.393 (9.98).236\" (6.0).224\" (6.2).319\" (8.1) BSC.050 (1.27) BSC0.513 (13.0)0.497 (12.6)0.105 (2.67)0.092 (2.34).026\" (0.65) BSC.378\"(9.6).386\"(9.8)0.012 (0.305)0.003 (0.076).002\" (0.05).006\" (0.15).043\" (1.10) MAX0REF80.013 (0.330)0.009 (0.229)0˚8˚REF.0035\" (0.09).0079\" (0.20).020\" (0.50).030\" (0.75)0.035 (0.8)0.015 (0.381)11

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