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TECHNICAL DATA
KK74HC273A
Octal D Flip-Flop with Common Clock and Reset
High-Performance Silicon-Gate CMOS
The KK74HC273A is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low.
• Outputs Directly Interface to CMOS, NMOS, and TTL
ORDERING INFORMATION • Operating Voltage Range: 2.0 to 6.0 V
KK74HC273AN Plastic • Low Input Current: 1.0 µA
KK74HC273ADW SOIC • High Noise Immunity Characteristic of CMOS Devices
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=VCC PIN 10 = GND
Inputs Output ResetClockD Q L L X X
H H H H L L H L X no changeH X no changeX = don’t care
1
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KK74HC273A
MAXIMUM RATINGS*
Symbol Parameter VCCVINVOUTIINIOUTICCPDTstg TL
*
Value Unit -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5
±20 ±35 ±75 750 500 -65 to +150
260
V V V mA mA mA mW °C °C
DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin
DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
VCCVIN, VOUT
TAtr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC =2.0 V VCC =4.5 V VCC =6.0 V
2.0 0 -55 0 0 0
6.0 VCC+125 1000 500 400
V V °C ns
Symbol Parameter Min Max Unit
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
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KK74HC273A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
≤85 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0
≤125 °C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0
Unit
Symbol Parameter Test Conditions V 25 °C
to -55°C
2.04.56.02.04.56.02.04.56.0 4.56.02.04.56.0 4.56.06.06.0
1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage
VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA
VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA
V
VILV
VOH
Minimum High-VIN=VIH or VIL
Level Output Voltage ⎢IOUT⎢ ≤ 20 µA
VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA
V
VOL
Maximum Low-VIN= VIL or VIH
Level Output Voltage ⎢IOUT⎢ ≤ 20 µA
VIN= VIL or VIH ⎢IOUT⎢ ≤ 4.0 mA ⎢IOUT⎢ ≤ 5.2 mA VIN=VCC or GND VIN=VCC or GND IOUT=0µA
V
IINICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
µA
4.0 40 160 µA
3
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KK74HC273A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Unit
Symbol Parameter V 25 °C ≤85°C ≤125°C
to -55°Cfmax
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
Maximum Propagation Delay, Clock to Q (Figures 1 and 4)
Maximum Propagation Delay , Reset to Q (Figures 2 and 4)
Maximum Output Transition Time, Any Output (Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Enabled Output)
Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
2.04.56.02.04.56.02.04.56.02.04.56.0-
6.0 30 35 145 29 25 145 29 25 75 15 13 10
5.0 24 28 180 36 31 180 36 31 95 19 16 10
4.0 20 24 220 44 38 220 44 38 110 22 19 10
MHz
tPLH, tPHLns
tPHLns
tTLH, tTHLns
CIN
CPD
pF
Typical @25°C,VCC=5.0 V
48 pF TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
tSU
Minimum Setup Time, Data to Clock (Figure 3)
Minimum Hold Time, Clock to Data (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
Maximum Input Rise and Fall Times (Figure 1)
VCC2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
60 12 10 3.0 3.0 3.0 5.0 5.0 5.0 60 12 10 60 12 10 1000 500 400
Guaranteed Limit
≤85°C 75 15 13 3.0 3.0 3.0 5.0 5.0 5.0 75 15 13 75 15 13 1000 500 400
≤125°C 90 18 15 3.0 3.0 3.0 5.0 5.0 5.0 90 18 15 90 18 15 1000 500 400
Unit ns
Symbol Parameter V 25 °C to-55°C
thns
trecns
twns
twns
tr, tfns
4
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KK74HC273A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
5
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KK74HC273A
N SUFFIX PLASTIC DIP(MS - 001AD)ADimension, mm2011B110SymbolABCMIN24.6.1MAX26.927.115.33FLDF0.361.142.547.620°2.927.620.20.380.561.78C-T-SEATINGNGD0.25 (0.010) M TKPLANEGHHJMJKLMN10°3.818.260.36NOTES:1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.D SUFFIX SOIC(MS - 013AC)A2011Dimension, mmSymbolMIN12.67.42.350.330.41.279.530°0.10.23100.258°0.30.3210.650.75MAX137.62.650.511.27HBPAB1G10CR x 45CDF-T-D0.25 (0.010) M TCMKSEATINGPLANEJFMGHJKMPRNOTES:1. Dimensions A and B do not include mold flash or protrusion.2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. 6
