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专利名称：Method and apparatus for calibrating write
timing in a memory system
发明人：Thomas J. Giovannini,Alok Gupta,Ian
Shaeffer,Steven C. Woo
申请号：US15406373申请日：20170113公开号：US09881662B2公开日：20180130
专利附图：
摘要：A system that calibrates timing relationships between signals involved inperforming write operations is described. This system includes a memory controller
which is coupled to a set of memory chips, wherein each memory chip includes a phasedetector configured to calibrate a phase relationship between a data-strobe signal and aclock signal received at the memory chip from the memory controller during a writeoperation. Furthermore, the memory controller is configured to perform one or morewrite-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involvevarying a delay on the data-strobe signal relative to the clock signal by a multiple of aclock period.
申请人：Rambus Inc.
地址：Sunnyvale CA US
国籍：US
代理机构：Peninsula Patent Group
代理人：Lance Kreisman
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