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专利名称：Programmable delay for processor control
signals
发明人：Keith Krasnansky申请号：US10124673申请日：20020417公开号：US06771106B2公开日：20040803
专利附图：
摘要：A programmable delay circuit () maximizes processor bandwidth to externalperipherals by eliminating wait state addition as the only way for satisfying timingrequirements. Circuit () includes a programmable delay chain () connected to a hysteresis
circuit (). A processor control signal is fed into the programmable delay chain () whichincludes at least one switch () and at least one resistive element () connected together. Afirst feedback circuit () connects the output of the programmable delay chain () to theinput (IN) of the first embodiment () to keep the falling edge of the control signal thesame without any significant added delay. The hysteresis circuit () which provides a stablesignal connects to an output driver () for driving the processor control signal.
申请人：TEXAS INSTRUMENTS INCORPORATED
代理人：April M. Mosby,Wade James Brady, III,Frederick J. Telecky, Jr.
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