DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
1. General Description
The DM9000 is a fully integrated and cost-effectivesingle chip Fast Ethernet MAC controller with ageneral processor interface, a 10/100M PHY and 4KDword SRAM. It is designed with low power and highperformance process that support 3.3V with 5Vtolerance.
The DM9000 also provides a MII interface to connectHPNA device or other transceivers that support MIIinterface. The DM9000 supports 8-bit, 16-bit and 32-bit uP interfaces to internal memory accesses for
different processors. The PHY of the DM9000 caninterface to the UTP3, 4, 5 in 10Base-T and UTP5 in100Base-TX. It is fully compliant with the IEEE 802.3u Spec.Its auto-negotiation function will automatically configure theDM9000 to take the maximum advantage of its abilities. TheDM9000 also supports IEEE 802.3x full- duplex flow control.This programming of the DM9000 is very simple, so usercan port the software drivers to any system easily.
2. Block Diagram
LEDExternal MIIInterfaceEEPROMInterfacePHYceiver100 Base-TXtransceiverTX+/-10 Base-TTx/RxRX+/-100 Base-TXPCSMIIMACTX MachineControl &StatusRegisters MemoryManagementRX MachineInternalSRAMAutonegotiationMII ManagementControl& MII Register
Final
Version: DM9000-DS-F02June 26, 2002
ProcessorInterface1
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Table of Contents
1. General Description..............................................1
(22H~23H)..............................................................186.21 RX SRAM Write Pointer Address Register
(24H~25H).......................................................196.22 Vendor ID Register (28H~29H).......................196.23 Product ID Register (2AH~2BH).....................196.24 Chip Revision Register (2CH).........................196.25 Special Mode Control Register (2FH).............196.26 Memory Data Read Command without Address
Increment Register (F0H)................................196.27 Memory Data Read Command with Address
Increment Register (F2H)................................196.28 Memory Data Read_ address Register
(F4H~F5H) ......................................................196.29 Memory Data Write Command without Address
Increment Register (F6H)................................196.30 Memory Data Write Command with Address
Increment Register (F8H)................................196.31 Memory Data Write_ address Register
(FAH~FBH)......................................................206.32 TX Packet Length Register (FCH~FDH)........206.33 Interrupt Status Register (FEH)......................206.34 Interrupt Mask Register (FFH)........................20
2. Block Diagram………………………………………1
3. Features................................................................4
4. Pin Configuration..................................................54.1 Pin Configuration I: with MII Interface.................54.2 Pin Configuration II: with 32-Bit Data Bus...........6
5. Pin Description......................................................75.1 MII Interface........................................................75.2 Processor Interface.............................................85.3 EEPROM Interface.............................................95.4 Clock Interface....................................................95.5 LED Interface......................................................95.6 10/100 PHY/Fiber.............................................105.7 Miscellaneous Pins...........................................105.8 Power Pins........................................................10
7. EEPROM Format................................................21
6. Vendor Control and Status Register Set.............116.1 Network Control Register (00H)........................136.2 Network Status Register (01H).........................136.3 TX Control Register (02H)................................136.4 TX Status Register I (03H)................................146.5 TX Status Register II (04H)...............................146.6 RX Control Register (05H)................................146.7 RX Status Register (06H).................................156.8 Receive Overflow Counter Register (07H).......156.9 Back Pressure Threshold Register (08H).........156.10 Flow Control Threshold Register (09H)..........166.11 RX/TX Flow Control Register (0AH)...............166.12 EEPROM & PHY Control Register (0BH).......166.13 ROM & PHY Address Register (0CH)............176.14 EEPROM & PHY Data Register (0DH, 0EH)..176.15 Wake Up Control Register (0FH)....................176.16 Physical Address Register (10H~15H)...........176.17 Multicast Address Register (16H~1DH)..........186.18 General Purpose Control Register (1EH)…….186.19 General Purpose Register (1FH)....................186.20 TX SRAM Read Pointer Address Register
2
8. MII Register Description......................................228.1 Basic Mode Control Register (BMCR) – 00......238.2 Basic Mode Status Register (BMSR) – 01........248.3 PHY ID Identifier Register #1 (PHYID1) – 02...258.4 PHY Identifier Register #2 (PHYID2) – 03........258.5 Auto-negotiation Advertisement Register
(ANAR) – 04....................................................268.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) – 05................................................278.7 Auto-negotiation Expansion Register (ANER) –
06.....................................................................278.8 DAVICOM Specified Configuration Register
(DSCR) – 16.....................................................288.9 DAVICOM Specified Configuration and Status
Register (DSCSR) – 17...................................298.10 10BASE-T Configuration/Status (10BTCSR) –
18.....................................................................30
Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
9. Functional Description........................................319.1 Host Interface....................................................319.2 Direct Memory Access Control.........................319.3 Packet Transmission.........................................319.4 Packet Reception..............................................319.5 100Base-TX Operation.....................................329.5.1 4B5B Encoder................................................329.5.2 Scrambler.......................................................329.5.3 Parallel to Serial Converter............................329.5.4 NRZ to NRZI Encoder....................................329.5.5 MLT-3 Converter............................................329.5.6 MLT-3 Driver..................................................329.5.7 4B5B Code Group..........................................339.6 100Base-TX Receiver.......................................349.6.1 Signal Detect..................................................349.6.2 Adaptive Equalization....................................349.6.3 MLT-3 to NRZI Decoder.................................349.6.4 Clock Recovery Module.................................349.6.5 NRZI to NRZ..................................................349.6.6 Serial to Parallel.............................................349.6.7 Descrambler...................................................349.6.8 Code Group Alignment..................................359.6.9 4B5B Decoder................................................359.7 10Base-T Operation..........................................359.8 Collision Detection............................................359.9 Carrier Sense....................................................359.10 Auto-Negotiation.............................................359.11 Power Reduced Mode....................................369.11.1 Power Down Mode.......................................369.11.2 Reduced Transmit Power Mode..................36
11. Application Notes..............................................4311.1 Network Interface Signal Routing...................4311.2 10Base-T/100Base-TX Application Figure 11-1
.........................................................................4311.3 10Base-T/100Base-TX (Power Reduction
Application) Figure 11-2................................4411.4 Power Decoupling Capacitors Figure 11-3.....4511.5 Ground Plane Layout Figure 11-4..................4611.6 Power Plane Partitioning Figure 11-5.............4711.7 Magnetics Selection Guide.............................4811.8 Crystal Selection Guide Figure 11-6...............4811.9 Application of reverse MII Figure 11-7............49
12. Package Information.........................................5012.1 LQFP 100L Outline Dimensions.....................50
13. Appendix...........................................................51
14. Order Information..............................................53
10. DC and AC Electrical Characteristics...............3710.1 Absolute Maximum Rating (25∘C)................3710.2 Operating Conditions......................................3710.3 DC Electrical Characteristics..........................3810.4 AC Electrical Characteristics & Timing
Waveforms.......................................................3910.4.1 TP Interface.................................................3910.4.2 Oscillator/ Crystal Timing.............................3910.4.3 Processor Register Read Timing.................3910.4.4 Processor Register Write Timing.................4010.4.5 External MII Interface Transmit Timing........4110.4.6 External MII Interface Receive Timing.........4110.4.7 MII Management Interface Timing...............4210.4.8 EEPROM Interface Timing..........................42
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Version: DM9000-DS-F02June 26, 2002
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
3. Features
■Supports processor interface: byte/word/dword ofI/O command to internal memory data operation
■ Supports automatically load vendor ID and
product ID from EEPROM■ Supports 4 GPIO pins
■ Optional EEPROM configuration■ Very low power consumption mode:
– Power reduced mode (cable detection)– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
■ Compatible with 3.3V and 5.0V tolerant I/O■ 100-pin LQFP with CMOS process
■ Integrated 10/100M transceiver■ Supports MII and reverses MII interface■ Supports back pressure mode for half-duplex
mode flow control
■ IEEE802.3x flow control for full-duplex mode■ Supports wakeup frame, link status change and
magic packet events for remote wake up■ Integrated 4K dword SRAM
4
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Version: DM9000-DS-F02
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
4. Pin Configuration
4.1 Pin Configuration I: with MII Interface
75747372717069686766656362616059585756DGNDNCLINK_OWAKEUPPW_RST#DGNDSD15SD14SD13SD12SD11SD10SD9SD8DVDDIO16CMDSA4SA5SA6SA7SA8SA9DGNDINT7677787980818283848586878091929394959697991005554535251504948474544434241403938373635343332313029282726NCNCDVDDDVDDGPIO3GPIO2GPIO1GPIO0EECSEECKEEDOEEDIDGNDLINKACT#DUP#SPEED#CLK20MODGNDMDCMDIODVDDTX_ENTXD3TXD2TXD1DM9000TXD0TX_CLKTEST5RX_CLKRX_ERRX_DVCOLCRSDGNDRXD3RXD2RXD1RXD0LINK_IDVDDAVDDTXO-TXO+AGNDAGNDRXI-RXI+AVDDAVDDBGRES1234567101112131415161718192021222324Final
Version: DM9000-DS-F02June 26, 2002
IOR#IOW#AENIOWAITDVDDSD0SD1SD2SD3SD4SD5SD6SD7RSTDGNDTEST1TEST2TEST3TEST4DVDDX2_25MX1_25MDGNDSDAGND255
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
4.2 Pin Configuration II: with 32-Bit Data Bus
DGNDNCLINK_OWAKEUPPW_RST#DGNDSD15SD14SD13SD12SD11SD10SD9SD8DVDDIO16CMDSA4SA5SA6SA7SA8SA9DGNDINT76777879808182838485868780919293949596979910075747372717069686766656362616059585756555453525150494847454443424140393837363534333231302928272625NCNCDVDDDVDDGPIO3GPIO2GPIO1GPIO0EECSEECKEEDOEEDIDGNDLINKACT#DUP#SPEED#CLK20MODGNDIO32SD16DVDDNCSD17SD18SD19DM9000SD20SD21TEST5SD22SD23SD24SD25SD26DGNDSD27SD28SD29SD30SD31DVDDAVDDTXO-TXO+AGNDAGNDRXI-RXI+AVDDAVDDBGRESIOR#IOW#AENIOWAITDVDDSD0SD1SD2SD3SD4SD5SD6SD7RSTDGNDTEST1TEST2TEST3TEST4DVDDX2_25MX1_25MDGNDSDAGND1234567101112131415161718192021222324-
6
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Version: DM9000-DS-F02
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,LI= reset Latch Input, #= asserted low
5.1 MII Interface
Pin No.3741,40,39,
3843
Pin NameLINK_IRXD [3:0]CRS
I/OIII/O
External MII device link status
External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII modeExternal MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activitiesin 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.External MII Collision Detect. This pin is output in reverse MII interface.External MII Receive Data ValidExternal MII Receive ErrorExternal MII Receive Clock
External MII Transmit Clock. This pin is output in reverse MII interface.External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbpsnibble mode
TXD [2:0] is also used as the strap pins of IO base address.IO base = (strap pin value of TXD [2:0]) * 10H + 300HExternal MII Transmit EnableMII Serial Management Data
MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pinis high active
Description
4445474953,52,51,
50
COLRX_DVRX_ERRX_CLKTX_CLKTXD [3:0]
I/OIIII/OO
545657
TX_ ENMDIOMDC
OI/OO
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface
1
IOR#
I
Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.See the EEPROM content description for detailProcessor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.See the EEPROM content description for detailAddress Enable
A low active signal used to select the DM9000.
Processor Command Ready
When a command is issued before last command is completed, the IOWAIT willbe pulled low to indicate the current command is waited
7
2IOW#I
3AENI
4IOWAITO
Final
Version: DM9000-DS-F02June 26, 2002
146,7,8,9,10,11,12,13,,88,87,86,85,84,83,82
RST
I
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Hardware Reset Command, active high to reset the DM9000
SD0~15I/OProcessor Data Bus bit 0~15
93,94,95,96,97,98
SA4~9I
92CMDI
91IO16O
100INTO
SD16~31 (in56,53,52,
double word51,50,49,
mode)47,46,45,
44,43,41,40,39,38
3757IO32 (in double
word mode)
I/O
Address Bus 4~9
These pins are used to select the DM9000.
When SA9 and SA8 are in high states, and SA7 and AEN are in lowstates, and SA6~4 are matched with strap pins TXD2~0, the DM9000 isselected.
Command Type
When high, the access of this command cycle is DATA portWhen low, the access of this command cycle is ADDRESS portWord Command Indication
When the access of internal memory is word or dword width, this pin willbe asserted
This pin is low active at defaultInterrupt Request
This pin is high active at default, its polarity can be modified by EEPROMsetting or strap pin MDC. See the EEPROM content description for detailProcessor Data Bus bit 16~31
These pins are used as data bus bits 16~31 when the DM9000 is set todouble word mode (the straps pin EEDO is pulled high and WAKEUP isnot pull-high)
O
Double Word Command Indication
This pins is used as the double word command indication when theDM9000 is set to double data word mode, and this pin will be assertedwhen the access of internal memory is double word widthThis pin is low active at default
Note: The pins of processor interface except SD8,SD9 and IO16 are all have a pulled down resistor about 60k ohminternally
5.3 EEPROM Interface
EEDI
65
EEDO
II/O
Data from EEPROM
Data to EEPROM
This pin is also used as a strap pin. It combines with strap pin WAKEUP,and it can set the data width of the internal memory access
The decoder table is the following, where the logic 1 means the strap pinis pulled high
WAKEUP EEDO data width 0 0 16-bit 0 1 32-bit 1 0 8-bit 1 1 reserved
Final
Version: DM9000-DS-F02
June 26, 2002
8
6667
EECKEECS
OI/O
Clock to EEPROM
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21X2_25M
2259
X1_25MCLK20MO
OIO
Crystal 25MHz OutCrystal 25MHz In
20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHzThis pin has a pulled down resistor about 60k ohm internally.
5.5 LED Interface
60SPEED100#
O
61DUP#O
62LINK&ACT#O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or itis floating for the 10M mode of the internal PHYFull-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operatedin full-duplex mode, or it is floating for the half-duplex mode of the internalPHY
In LED mode 0, Its low output indicates that the internal PHY is operatedin 10M mode, or it is floating for the 100M mode of the internal PHYLink LED
In LED mode 1, it is the combined LED of link and carrier sense signal ofthe internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internalPHY only
5.6 10/100 PHY/Fiber
24SD
I
252627282930313233
BGGNDBGRESAVDDAVDDRXI+RXI-AGNDAGNDTXO+
PI/OPPIIPPO
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair isreceiving valid levelsBandgap GroundBandgap Pin
Bandgap and Guard Ring PowerRX PowerTP RX InputTP RX InputRX GroundTX GroundTP TX Output
9
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Version: DM9000-DS-F02June 26, 2002
3435
TXO-AVDD
OP
TP TX OutputTX Power
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
5.7 Miscellaneous
16,17,18,TEST1~TEST4
19
4868,69,70,
71
TEST5GPIO0~3
I
Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal applicationIt must be ground.
General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to powerdown internal PHY and other external MII deviceGPIO1~3 defaults are input ports
Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is areversed MII interface (pulled high) or a normal MII interface (not pulledhigh). This pin has a pulled down resistor about 60k ohm internally.Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.Power on Reset
Active low signal to initiate the DM9000
The DM9000 is ready after 5us when this pin deassertedNot Connect
II/O
78LINK_OO
7980
WAKEUPPW_RST#
OI
74,75,77NC
5.8 Power Pins
DVDD5,20,36,
55,72,90,
7315,23,42,DGND58,63,81,99,76
PDigital VDD
PDigital GND
10
Final
Version: DM9000-DS-F02
June 26, 2002
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6. Vendor Control and Status Register Set
The DM9000 implements several control and status
registers, which can be accessed by the host. These CSRsRegisterNCRNSRTCRTSR ITSR IIRCRRSRROCRBPTRFCTRFCREPCREPAREPDRLEPDRHWCRPARMARGPCRGPRTRPALTRPAHRWPALRWPAHVIDPIDCHIPRSMCRMRCMDXMRCMDMRRLMRRHMWCMDXMWCMDMWRL
Description
Network Control RegisterNetwork Status RegisterTX Control RegisterTX Status Register ITX Status Register IIRX Control RegisterRX Status Register
Receive Overflow Counter RegisterBack Pressure Threshold RegisterFlow Control Threshold RegisterRX Flow Control Register
EEPROM & PHY Control RegisterEEPROM & PHY Address Register
EEPROM & PHY Low Byte Data RegisterEEPROM & PHY High Byte Data RegisterWake Up Control RegisterPhysical Address Register
Multicast Address Register
General Purpose Control RegisterGeneral Purpose Register
TX SRAM Read Pointer Address Low ByteTX SRAM Read Pointer Address High ByteRX SRAM Write Pointer Address Low ByteRX SRAM Write Pointer Address High ByteVendor IDProduct IDCHIP Revision
Special Mode Control Register
Memory Data Read Command Without Address IncrementRegister
Memory Data Read Command With Address IncrementRegister
Memory Data Read_ address Register Low ByteMemory Data Read_ address Register High Byte
Memory Data Write Command Without Address IncrementRegister
Memory Data Write Command With Address IncrementRegister
Memory Data Write_ address Register Low Byte
are byte aligned. All CSRs are set to their default values byhardware or software reset unless they are specified
Offset00H01H02H03H04H05H06H07H08H09H0AH0BH0CH0DH0EH0FH10H-15H16H-1DH1EH1FH22H23H24H25H28H-29H2AH-2BH2CH2FHF0HF2HF4HF5HF6HF8HFAH
Default valueafter reset00H00H00H00H00H00H00H00H37H38H00H00H40HXXHXXH00H
Determined byEEPROMXXH01HXXH00H00H04H0CH0A46H9000H00H00HXXHXXH00H00HXXHXXH00H
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Version: DM9000-DS-F02June 26, 2002
MWRHTXPLLTXPLHISRIMR
Memory Data Write _ address Register High ByteTX Packet Length Low Byte RegisterTX Packet Length High Byte RegisterInterrupt Status RegisterInterrupt Mask Register
FBHFCHFDHFEHFFH
DM9000
00HXXHXXH00H00H
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Key to Default
In the register description that follows, the default columntakes the form:
RW/C1=Read/Write and Cleared by write 1WO = Write only Reserved bits are shaded and should be written with 0.Reserved bits are undefined on read access. 12 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.1 Network Control Register (00H)BitNameDefaultDescription7EXT_PHY0,RWSelects external PHY when set. Selects Internal PHY when clear. This bit will not be affected after software reset 6WAKEEN0,RWWakeup Event Enable When set, it enables the wakeup function. Clearing this bit will also clears allwakeup event status This bit will not be affected after a software reset 5RESERVED0,ROReserved4FCOL0,RWForce Collision Mode, used for testing3FDX0,RWFull-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode2:1LBK00,RWLoopback Mode Bit 2 1 0 0 Normal 0 1 MAC Internal loopback 1 0 Internal PHY 100M mode digital loopback 1 1 (Reserved) 0RST0,RWSoftware reset and auto clear after 10us6.2 Network Status Register (01H)BitNameDefault7SPEED0,RO 6543210 LINKSTWAKESTRESERVEDTX2ENDTX1ENDRXOVRESERVED 0,RO0,RW/C10,RO0,RW/C10,RW/C10,RO0,RO Description Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has nomeaning when LINKST=0 Link Status 0:link failed 1:link OK, when Internal PHY is usedWakeup Event Status. Clears by read or write 1This bit will not be affected after software resetReserved TX Packet 2 Complete Status. Clears by read or write 1Transmit completion of packet index 2 TX Packet 1 Complete status. Clears by read or write 1Transmit completion of packet index 1RX FIFO OverflowReserved 6.3 TX Control Register (02H)BitNameDefault7RESERVED0,RO 6543210 TJDISEXCECMPAD_DIS2CRC_DIS2PAD_DIS1CRC_DIS1TXREQ 0,RW0,RW0,RW0,RW0,RW0,RW0,RW Description Reserved Transmit Jabber Disable When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is EnableExcessive Collision Mode Control : 0:aborts this packet when excessive collisioncounts more than 15, 1: still tries to transmit this packetPAD Appends Disable for Packet Index 2CRC Appends Disable for Packet Index 2PAD Appends Disable for Packet Index 1CRC Appends Disable for Packet Index 1 TX Request. Auto clears after sending completely Final Version: DM9000-DS-F02June 26, 2002 13 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.4 TX Status Register I ( 03H ) for packet index IBitNameDefaultDescription7TJTO0,ROTransmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048bytes are transmitted 6LC0,ROLoss of Carrier It is set to indicate the loss of carrier during the frame transmission. It is not valid ininternal loopback mode 5NC0,RONoCarrier It is set to indicate that there is no carrier signal during the frame transmission. It isnot valid in internal loopback mode 4LC0,ROLate Collision It is set when a collision occurs after the collision window of bytes 3COL0,ROCollision Packet It is set to indicate that the collision occurs during transmission 2EC0,ROExcessive Collision It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0RESERVED0,ROReserved 6.5 TX Status Register II ( 04H ) for packet index I IBitNameDefaultDescription7TJTO0,ROTransmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048bytes are transmitted 6LC0,ROLoss of Carrier It is set to indicate the loss of carrier during the frame transmission. It is not valid ininternal loopback mode 5NC0,RONoCarrier It is set to indicate that there is no carrier signal during the frame transmission. It isnot valid in internal loopback mode 4LC0,ROLate Collision It is set when a collision occurs after the collision window of bytes 3COL0,ROCollision packet, collision occurs during transmission2EC0,ROExcessive Collision It is set to indicate that the transmission is aborted due to 16 excessive collisions 1:0RESERVED0,ROReserved6.6 RX Control Register ( 05H )BitNameDefault7RESERVED0,RO WTDIS0,RW6 54 3210 14 Description Reserved Watchdog Timer Disable When set, the Watchdog Timer (2048 bytes) is disabled. Otherwise it is enabledDiscard Long Packet Packet length is over 1522byteDiscard CRC Error PacketPass All MulticastPass Runt PacketPromiscuous ModeRX Enable Final Version: DM9000-DS-F02 June 26, 2002 DIS_LONGDIS_CRCALLRUNTPRMSCRXEN 0,RW0,RW0,RW0,RW0,RW0,RW DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.7 RX Status Register ( 06H )BitNameDefault7RF0,RO 6543210 MFLCSRWTOPLEAECEFOE 0,RO0,RO0,RO0,RO0,RO0,RO0,RO Description Runt Frame It is set to indicate that the size of the received frame is smaller than bytesMulticast Frame It is set to indicate that the received frame has a multicast addressLate Collision Seen It is set to indicate that a late collision is found during the frame receptionReceive Watchdog Time-Out It is set to indicate that it receives more than 2048 bytesPhysical Layer Error It is set to indicate that a physical layer error is found during the frame receptionAlignment Error It is set to indicate that the received frame ends with a non-byte boundaryCRC Error It is set to indicate that the received frame ends with a CRC errorFIFO Overflow Error It is set to indicate that a FIFO overflow error happens during the frame reception 6.8 Receive Overflow Counter Register ( 07H )BitNameDefaultDescription7RXFU0,R/CReceive Overflow Counter Overflow This bit is set when the ROC has an overflow condition 6:0ROC0,R/CReceive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow6.9 Back Pressure Threshold Register (08H)BitNameDefaultDescription7:4BPHW3H, RWBack Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold valueDefault is 3K-byte free space. Please do not exceed SRAM size(1 unit=1K bytes) 3:0JPT7H, RWJam Pattern Time. Default is 200us bit3 bit2 bit1 bit0 time 0 0 0 0 5us 0 0 0 1 10us 0 0 1 0 15us 0 0 1 1 25us 0 1 0 0 50us 0 1 0 1 100us 0 1 1 0 150us 0 1 1 1 200us 1 0 0 0 250us 1 0 0 1 300us 1 0 1 0 350us 1 0 1 1 400us 1 1 0 0 450us 1 1 0 1 500us 1 1 1 0 550us 1 1 1 1 600us Final Version: DM9000-DS-F02June 26, 2002 15 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.10 Flow Control Threshold Register ( 09H )BitNameDefaultDescription7:4HWOT3H, RWRX FIFO High Water Overflow Threshold Send a pause packet with pause_ time=FFFFH when the RX RAM free space isless than this value., If this value is zero, its means no free RX SRAM space. Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) 3:0LWOT8H, RWRX FIFO Low Water Overflow Threshold Send a pause packet with pause_time=0000 when RX SRAM free space is largerthan this value. This pause packet is enabled after the high water pause packet istransmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM size(1 unit=1K bytes)6.11 RX/TX Flow Control Register ( 0AH )BitNameDefaultDescription7TXP00,RWTX Pause Packet Auto clears after pause packet transmission completion. Set to TX pause packetwith time = 0000h 6TXPF0,RWTX Pause packet Auto clears after pause packet transmission completion. Set to TX pause packetwith time = FFFFH 5TXPEN0,RWForce TX Pause Packet Enable Enables the pause packet for high/low water threshold control 4BKPA0,RWBack Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when any packetcomes and RX SRAM is over BPHW 3BKPM0,RWBack Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when a packet’sDA matches and RX SRAM is over BPHW 2RXPS0,R/CRX Pause Packet Status, latch and read clearly1RXPCS0,RORX Pause Packet Current Status0FLCE0,RWFlow Control Enable Set to enable the flow control mode (i.e. to disable TX function)6.12 EEPROM & PHY Control Register ( 0BH ) BitNameDefaultDescription7:6RESERVED0,ROReserved5REEP0,RWReload EEPROM. Driver needs to clear it up after the operation completes4WEP0,RWWrite EEPROM Enable3EPOS0,RWEEPROM or PHY Operation Select When reset, select EEPROM; when set, select PHY 2ERPRR0,RWEEPROM Read or PHY Register Read Command. Driver needs to clear it up after the operation completes. 1ERPRW0,RWEEPROM Write or PHY Register Write Command. Driver needs to clear it up after the operation completes. 0ERRE0,ROEEPROM Access Status or PHY Access Status When set, it indicates that the EEPROM or PHY access is in progress 16 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.13 EEPROM & PHY Address Register ( 0CH )BitNameDefaultDescription7:6PHY_ADR01,RWPHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if internal PHY is selected 5:0EROA0,RWEEPROM Word Address or PHY Register Address6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH EE_PHY_H：0EH)BitNameDefaultDescription7:0EE_PHY_LX,RWEEPROM or PHY Low Byte Data This data is made to write low byte of word address defined in Reg. CH toEEPROM or PHY 7:0EE_PHY_HX,RWEEPROM or PHY High Byte Data This data is made to write high byte of word address defined in Reg. CH toEEPROM or PHY6.15 Wake Up Control Register ( 0FH )BitNameTypeDescription7:6RESERVED0,ROReserved5LINKEN0,RWWhen set, it enables Link Status Change Wake up Event This bit will not be affected after software reset 4SAMPLEEN0,RWWhen set, it enables Sample Frame Wake up Event This bit will not be affected after software reset 3MAGICEN0,RWWhen set, it enables Magic Packet Wake up Event This bit will not be affected after software reset 2LINKST0,ROWhen set, it indicates that Link Change and Link Status Change Event occurred This bit will not be affected after software reset 1SAMPLEST0,ROWhen set, it indicates that the sample frame is received and Sample Frame Event occurred. This bit will not be affected after software reset 0MAGICST0,ROWhen set, indicates the Magic Packet is received and Magic packet Event occurred. This bit will not be affected after a software reset6.16 Physical Address Register ( 10H~15H )BitNameDefault7:0PAB5X,RWPhysical Address Byte 5 (15H)7:0PAB4X,RWPhysical Address Byte 4 (14H)7:0PAB3X,RWPhysical Address Byte 3 (13H)7:0PAB2X,RWPhysical Address Byte 2 (12H)7:0PAB1X,RWPhysical Address Byte 1 (11H)7:0PAB0X,RWPhysical Address Byte 0 (10H) Description Final Version: DM9000-DS-F02June 26, 2002 17 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.17 Multicast Address Register ( 16H~1DH )BitNameDefaultDescription7:0MAB7X,RWMulticast Address Byte 7 (1DH)7:0MAB6X,RWMulticast Address Byte 6 (1CH)7:0MAB5X,RWMulticast Address Byte 5 (1BH)7:0MAB4X,RWMulticast Address Byte 4 (1AH)7:0MAB3X,RWMulticast Address Byte 3 (19H)7:0MAB2X,RWMulticast Address Byte 2 (18H)7:0MAB1X,RWMulticast Address Byte 1 (17H)7:0MAB0X,RWMulticast Address Byte 0 (16H) 6.18 General purpose control Register ( 1EH )BitNameDefaultDescription7:4RESERVED0,ROReserved3:0GEP_CNTL0001,RWGeneral Purpose Control Define the input/output direction of General Purpose Register When a bit is set 1, the direction of correspondent bit of General Purpose Registeris output. GPIO0 default is output for POWER_DOWN function. Other defaults areinput6.19 General purpose Register ( 1FH )BitNameDefaultDescription7:4RESERVED0,ROReserved3:1GEPIO3-10,RWGeneral Purpose When the correspondent bit of General Purpose Control Register is 1, the value ofthe bit is reflected to pin GEPIO3-1 When the correspondent bit of General Purpose Control Register is 0, the value ofthe bit to be read is reflected from correspondent pins of GEPIO3-1The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively 0GEPIO01,RWGeneral Purpose When the correspondent bit of General Purpose Control Register is 1, the value ofthe bit is the output to pin GEPIO0 When the correspondent bit of General Purpose Control Register is 0, the value ofthe bit to be read is reflected from pin GEPIO0. GEPIO0 default output 1 to POWER_DOWN Internal PHY. Driver needs to clear this POWER_DOWN signalby writing “0” when it wants PHY to be active. This default value can beprogrammed by EEPROM. Please refer to the EEPROM description6.20 TX SRAM Read Pointer Address Register (22H~23H)BitNameDefaultDescription7:0TRPAH00H,ROTX SRAM Read Pointer Address High Byte (23H)7:0TRPAL00H.ROTX SRAM Read Pointer Address Low Byte (22H)6.21 RX SRAM Write Pointer Address Register (24H~25H)BitNameDefaultDescription7:0RWPAH0CH,RORX SRAM Write Pointer Address High Byte (25H)7:0RWPAL04H.RORX SRAM Write Pointer Address Low Byte (24H) 18 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.22 Vendor ID Register (28H~29H)BitNameDefault7:0VIDH0AH,RO7:0VIDL46H.RO Description Vendor ID High Byte (29H) Vendor ID Low Byte (28H) 6.23 Product ID Register (2AH~2BH)BitNameDefault7:0PIDH90H,ROProduct ID High Byte (2BH)7:0PIDL00H.ROProduct ID Low Byte (2AH)6.24 Chip Revision Register (2CH)BitNameDefault7:0CHIPR00H,RO Description Description CHIP Revision 6.25 Special Mode Control Register ( 2FH )BitNameDefault7SM_EN0,RWSpecial Mode Enable6~3RESERVED0,ROReserved2FLC0,RWForce Late Collision1FB10,RWForce Longest Back-off time0FB00,RWForce Shortest Back-off time Description 6.26 Memory Data Read Command without Address Increment Register (F0H)BitNameDefaultDescription7:0MRCMDXX,RORead data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged6.27 Memory Data Read Command with Address Increment Register (F2H)BitNameDefaultDescription7:0MRCMDX,RORead data from RX SRAM. After the read of this command, the read pointer is increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bitrespectively)6.28 Memory Data Read_address Register (F4H~F5H)BitNameDefaultDescription7:0MDRAH00H,R/WMemory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =17:0MDRAL00H,R/WMemory Data Read_ address Low Byte6.29 Memory Data Write Command without Address Increment Register (F6H)BitNameDefaultDescription7:0MWCMDXX,WOWrite data to TX SRAM. After the write of this command, the write pointer is unchanged Final Version: DM9000-DS-F02June 26, 2002 19 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.30 Memory data write command with address increment Register (F8H)BitNameDefaultDescription7:0MWCMDX,WOWrite Data to TX SRAM After the write of this command, the write pointer is increased by 1,2, or 4, dependson the operator mode. (8-bit, 16-bit,32-bit respectively)6.31 Memory data write_address Register (FAH~FBH)BitNameDefaultDescription7:0MDRAH00H,R/WMemory Data Write_ address High Byte7:0MDRAL00H,R/WMemory Data Write_ address Low Byte6.32 TX Packet Length Register (FCH~FDH)BitNameDefault7:0TXPLHX,R/WTX Packet Length High byte7:0TXPLLX,,R/WTX Packet Length Low byte Description 6.33 Interrupt Status Register (FEH)BitNameDefaultDescription7:6IOMODE0, ROBit 7 Bit 6 0 0 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 Reserved 5~4RESERVED0,ROReserved3ROOS0,RW/C1Receive Overflow Counter Overflow Latch2ROS0,RW/C1Rx Overflow Latch1PTS0,RW/C1Packet Transmitted Latch0PRS0,RW/C1Packet Received Latch6.34 Interrupt Mask Register (FFH)BitNameDefault7PAR0,RW6~43210 RESERVEDROOMROMPTMPRM 0,RO0,RW0,RW0,RW0,RW Description Enable the SRAM read/write pointer to automatically return to the start addresswhen pointer addresses are over the SRAM size. Driver needs to set. When driversets this bit, REG_F5 will set to 0Ch automaticallyReserved Enable Receive Overflow Counter Overflow LatchEnable RX Overflow Latch Enable Packet Transmitted LatchEnable Packet Received Latch 20 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 7. EEPROM Format nameMAC addressAuto Load Control Word03 offsetDescription0~56 Byte Ethernet Address6-7Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0]Bit 5:4=01: Accept setting of WORD6 [11:9]Bit 7:6=01: Accept setting of WORD7 [3:0]Bit 9:8=01: Accept setting of WORD7 [6:4]Bit 11:10=01: Accept setting of WORD7 [7]Bit 13:12=01: Accept setting of WORD7 [8]Bit 15:14=01: reserved8-92 byte vendor ID (Default: 0A46H)10-112 byte product ID (Default: 9000H) 12-13When word 3 bit [3:2]=01, these bits can control the IOR, IOW and INT pins polarity. Bit0: Reserved Bit1: IOR pin is active low when set (default: active low)Bit2: IOW pin is active low when set (default: active low)Bit3: INT pin is active low when set (default: active high)Bit4: INT pin s open-collected (default: force output)Bit5: ReservedBit6: ReservedBit7: ReservedBit8: Reserved When word 3 bit [5:4]=01, the I/O base can be re-configured. Bit11:09: I/O base (default: 300H) 000 : 300H001 : 310H010 : 320H011 : 330H100 : 340H101 : 350H110 : 360H111 : 370HBit15:12: reserved Depend on the setting of word 3: Bit0: The WAKEUP pin is active low when set (default: active high)Bit1: The WAKEUP pin is in pulse mode when set (default: level mode)Bit2: magic wakeup event is enabled when set. (default: no))Bit3: link_change wakeup event is enabled when set (default: no)Bit6:4: reserved Bit7: LED mode 1 (default: 0) Bit8: internal PHY is enabled after power-on (default: no) The GPR bit 0 and the GPIO0 pin are modified from this bit.Bit15:9: reserved Vendor IDProduct IDpin control456 Wake-up mode control714-15 RESERVEDRESERVED Final Version: DM9000-DS-F02June 26, 2002 16-1718-19 21 RESERVEDRESERVED 1011 20-2122-23 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 8. MII Register Description ADName15D 00CONTROLReset01 STATUS T4Cap.01NextPageLPNextPage 14LoopbackTX FDXCap.00FLP RcvAckLPAck 13121110Isolate987Coll.Test Pream.Supr.0Auto-NCompl.0RemoteFault06543ReservedLinkJabberStatusDetect00Version No.Advertised Protocol Selector FieldLink Partner Protocol Selector FieldAuto-NCap.0ExtdCap.0210SpeedAuto-NPowerSelectEnableDownTX HDX10 FDX10 HDXCap.Cap.Cap.000111RemoteReservedFaultLPReservedRF RestartFullAuto-NDuplex Reserved0T4AdvLPT4 102PHYID103PHYID204Auto-Neg. Advertise05Link Part. Ability06Auto-Neg. Expansion16SpecifiedConfig.17Specified Conf/Stat1810T Conf/Stat 00FCAdvLPFCReserved 1Model No.TX FDXTX HDX10 FDX10 HDXAdvAdvAdvAdvLPLPLPLPTX FDXTX HDX10 FDX10 HDX PardetFault RsvdRsvdForceReserved100LNK PHY ADDR [4:0] LP NextPg AbleNext PgAbleNew PgRcv BP4B5B100FDXRsvd BPSCR100HDXLPEnableBPBP_ADRsvdTXALIGNPOK1010 HDXReservedFDXHBESQUEJAB10TEnableEnableEnableSerial RPDCTRReset-ENSt. Mch Pream.SleepSupr.modeAuto-N. Monitor Bit [3:0] LPAutoNCap.RemoteLoopOut Reserved PolarityReverse Key to Default In the register description that follows, the defaultcolumn takes the form: 1Bit set to logic one0Bit set to logic zeroXNo default value (PIN#)Value latched from pin # at reset RO = Read OnlyRW = Read/Write SC = Self Clearing P = Value Permanently SetLL = Latching LowLH = Latching High 22 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC controller with integrated 10/100 PHY 8.1 Basic Mode Control Register (BMCR) - 00 BitBit NameDefaultDescription0.15Reset0, RW/SCReset 1=Software reset0=Normal operation This bit sets the status and controls the PHY registers to their defaultstates. This bit, which is self-clearing, will keep returning a value ofone until the reset process is completed 0.14Loopback0, RWLoopback Loop-back control register1 = Loop-back enabled0 = Normal operation In 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms \"deadtime\" before any valid data appears at the MII receive outputs 0.13Speed selection1, RWSpeed Select 1 = 100Mbps0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation.When auto-negotiation is enabled and bit 12 is set, this bit will returnto the auto-negotiation selected media type 1, RWAuto-negotiation Enable0.12Auto-1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation negotiation statusenable 0.11Power down0, RWPower Down While in the power-down state, the PHY should respond to the management transactions. During the transition to power-down stateand while in the power-down state, the PHY should not generatespurious signals on the MII1=Power down 0=Normal operation 0.10Isolate0,RWIsolate 1 = Isolates the PHY from the MII with the exception of the serialmanagement. (When this bit is asserted, the PHY does not respondto the TXD [0:3], TX_EN, and TX_ER inputs, and it shall present ahigh impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[0:3], COL and CRS outputs. When PHY is isolated from the MIIit shall respond to the management transactions)0 = Normal operation 0.9Restart auto-0,RW/SCRestart Auto-negotiation negotiation1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this registercleared), this bit has no function and it should be cleared. This bit isself-clearing and it will keep returning a value of 1 until auto-negotiation is initiated by the PHY. The operation of the auto-negotiation process will not be affected by the management entitythat clears this bit0 = Normal operation Final Version: DM9000-DS-F01April 12, 2002 23 0.8 Duplex mode 1,RW DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). Withenabled auto-negotiation, this bit reflects the duplex capabilityselected by auto-negotiation0 = Normal operationCollision Test 1 = Collision test is enabled. When set, this bit will cause the COLsignal to be asserted in response to the assertion of TX_EN0 = Normal operationReserved Write as 0, ignore on read 0.7Collision test0,RW 0.6-0.0RESERVED0,RO 8.2 Basic Mode Status Register (BMSR) - 01 BitBit NameDefaultDescription1.15100BASE-T40,RO/P100BASE-T4 Capable 1 = Able to perform in 100BASE-T4 mode0 = Not able to perform in 100BASE-T4 mode 1.14100BASE-TX1,RO/P100BASE-TX Full Duplex Capable full duplex1 = Able to perform 100BASE-TX in full duplex mode 0 = Not able to perform 100BASE-TX in full duplex mode 1.13100BASE-TX1,RO/P100BASE-TX Half Duplex Capable half duplex1 = Able to perform 100BASE-TX in half duplex mode 0 = Not able to perform 100BASE-TX in half duplex mode 1.1210BASE-T1,RO/P10BASE-T Full Duplex Capable full duplex1 = Able to perform 10BASE-T in full duplex mode 0 = Not able to perform 10BASE-TX in full duplex mode 1.1110BASE-T1,RO/P10BASE-T Half Duplex Capable half duplex1 = Able to perform 10BASE-T in half duplex mode 0 = Not able to perform 10BASE-T in half duplex mode 1.10-1.7RESERVED0,ROReserved Write as 0, ignore on read 1.6MF preamble0,ROMII Frame Preamble Suppression suppression1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamblesuppressed 0,ROAuto-negotiation Complete1.5Auto-1 = Auto-negotiation process completednegotiation 0 = Auto-negotiation process not completedComplete 1.4Remote fault0,Remote Fault 0,RO/LH1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is specific PHY implementation. This bit will set after the RF bit in the ANLPAR (bit13, register address 05) is set 0 = No remote fault condition detected 1,RO/PAuto Configuration Ability1.3Auto-1 = Able to perform auto-negotiationnegotiation 0 = Not able to perform auto-negotiationAbility 1.2Link status0,RO/LLLink Status 1 = Valid link is established (for either 10Mbps or 100Mbps 24 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY operation) 0 = Link is not established The link status bit is implemented with a latching function, so that theoccurrence of a link failure condition causes the link status bit to be,and remain cleared until it is read via the management interfaceJabber Detect 1 = Jabber condition detected0 = No jabber This bit is implemented with a latching function. Jabber conditionswill set this bit unless it is cleared by a read to this register through amanagement interface or a PHY reset. This bit works only in 10Mbpsmode Extended Capability 1 = Extended register capable0 = Basic register capable only 1.1Jabber detect 0,RO/LH 1.0Extendedcapability 1,RO/P 8.3 PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000. The Identifier consistsof a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a modelrevision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606EBit2.15-2.0 Bit NameOUI_MSB Default<0181H> Description OUI Most Significant Bits Bit 3 to 18 of the OUI (00606E) are mapped to bit 15 to 0 of thisregister respectively. The most significant two bits of the OUI areignored (the IEEE standard refers to these as bit 1 and 2) 8.4 PHY Identifier Register #2 (PHYID2) - 03 BitBit NameDefaultDescription3.15-3.10OUI_LSB<101110>,OUI Least Significant Bits RO/PBit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively 3.9-3.4VNDR_MDL<001100>,Vendor Model Number RO/PSix bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3.3-3.0MDL_REV<0000>,Model Revision Number RO/PFour bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3) Final Version: DM9000-DS-F02June 26, 2002 25 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9000 device as they will be transmitted to its link partnerduring Auto-negotiation.Bit4.15 Bit NameNP Default0,RO/P Description 4.14ACK 4.134.12-4.114.104.9 RFRESERVED FCST4 4.84.74..54.4-4.0 TX_FDXTX_HDX10_FDX10_HDXSelector Next Page Indication 0 = No next page available1 = Next page available The PHY has no next page, so this bit is permanently set to 0 0,ROAcknowledge 1 = Link partner ability data reception acknowledged0 = Not acknowledged The PHY's auto-negotiation state machine will automaticallycontrol this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Softwareshould not attempt to write to this bit 0, RWRemote Fault 1 = Local device senses a fault condition0 = No fault detected X, RWReserved Write as 0, ignore on read 0, RWFlow Control Support 1 = Controller chip supports flow control ability 0 = Controller chip doesn’t support flow control ability 0, RO/P100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device0 = 100BASE-T4 is not supported The PHY does not support 100BASE-T4 so this bit is permanentlyset to 0 1, RW100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device0 = 100BASE-TX full duplex is not supported 1, RW100BASE-TX Support 1 = 100BASE-TX is supported by the local device0 = 100BASE-TX is not supported 1, RW10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the local device0 = 10BASE-T full duplex is not supported 1, RW10BASE-T Support 1 = 10BASE-T is supported by the local device0 = 10BASE-T is not supported <00001>, RWProtocol Selection Bits These bits contain the binary encoded protocol selector supportedby this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD 26 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiationBit5.155.14 Bit NameNPACK Default0, RO Description 5.135.12-5.115.10 RFRESERVED FCS 5.95.85.75.65.55.4-5.0 T4TX_FDXTX_HDX10_FDX10_HDXSelector Next Page Indication 0 = Link partner, no next page available1 = Link partner, next page available 0, ROAcknowledge 1 = Link partner ability data reception acknowledged0 = Not acknowledged The PHY's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should notattempt to write to this bit 0, RORemote Fault 1 = Remote fault indicated by link partner0 = No remote fault indicated by link partner X, ROReserved Write as 0, ignore on read 0, RWFlow Control Support 1 = Controller chip supports flow control ability by link partner0 = Controller chip doesn’t support flow control ability by linkpartner 0, RO100BASE-T4 Support 1 = 100BASE-T4 is supported by the link partner0 = 100BASE-T4 is not supported by the link partner 0, RO100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the link partner0 = 100BASE-TX full duplex is not supported by the link partner 0, RO100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the link partner0 = 100BASE-TX half duplex is not supported by the link partner 0, RO10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the link partner0 = 10BASE-T full duplex is not supported by the link partner 0, RO10BASE-T Support 1 = 10BASE-T half duplex is supported by the link partner0 = 10BASE-T half duplex is not supported by the link partner <00000>, ROProtocol Selection Bits Link partner’s binary encoded protocol selector 8.7 Auto-negotiation Expansion Register (ANER)- 066.15-6.5RESERVEDX, ROReserved Write as 0, ignore on read 6.4PDF0, RO/LHLocal Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function.PDF = 0: No fault detected via parallel detection function 6.3LP_NP_ABLE0, ROLink Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page availableLP_NP_ABLE = 0: Link partner, no next page 6.2NP_ABLE0,RO/PLocal Device Next Page Able Final Version: DM9000-DS-F02June 26, 2002 27 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 6.1 PAGE_RX 0, RO/LH NP_ABLE = 1: next page availableNP_ABLE = 0: no next pageNew Page Received A new link of code-word page received. This bit will be automatically cleared when the register (register 6) is read bymanagement Link Partner Auto-negotiation Able A “1” in this bit indicates that the link partner supports Auto-negotiation 6.0LP_AN_ABLE0, RO 8.8 DAVICOM Specified Configuration Register (DSCR) - 16 BitBit NameDefaultDescription16.15BP_4B5B0, RWBypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed0 = Normal 4B5ccccccccB and 5B4B operation 16.14BP_SCR0, RWBypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed0 = Normal scrambler and descrambler operation 16.13BP_ALIGN0, RWBypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symboldecoding functions) bypassed. Transmit functions(symbol encoder and scrambler) bypassed0 = Normal operation 16.12BP_ADPOK0, RWBypass ADPOK Force signal detector (SD) active. This register is for debug only,not release to customers.1=Force SD is OK0=Normal operation 16.11RESERVED0, ROReserved Write as 0, ignore on read 16.10TX1, RO100BASE-TX 1 = 100BASE-TX operation0 = Reserved 16.9RESERVED0, ROReserved16.8RESERVED0, ROReserved Write as 0, ignore on read 16.7F_LINK_1000, RWForce Good Link in 100Mbps 0 = Normal 100Mbps operation 1 = Force 100Mbps good link statusThis bit is useful for diagnostic purposes 16.6RESERVED0, ROReserved Write as 0, ignore on readReserved 16.5RESERVED0, RO Write as 0, ignore on read Reduced Power Down Control Enable 16.4RPDCTR-EN1, RW This bit is used to enable automatic reduced power down0: Disable automatic reduced power down1: Enable automatic reduced power downReset State Machine 16.3SMRST0, RWWhen writes 1 to this bit, all state machines of PHY will be reset. 28 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 16.2 MFPSC 0, RW This bit is self-clear after reset is completedMF Preamble Suppression Control MII frame preamble suppression control bit1 = MF preamble suppression bit on0 = MF preamble suppression bit offSleep Mode Writing a 1 to this bit will cause PHY to enter the Sleep mode andpower down all circuit except oscillator and clock generator circuit.When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the statemachine will be resetRemote Loopout Control When this bit is set to 1, the received data will loop out to thetransmit channel. This is useful for bit error rate testing 16.1SLEEP0, RW 16.0RLOUT0, RW 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 BitBit NameDefaultDescription17.15100FDX1, RO100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit.If this bit is 1, it means the operation 1 mode is a 100M full duplexmode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in theauto-negotiation mode 17.14100HDX1, RO100M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit.If this bit is 1, it means the operation 1 mode is a 100M half duplexmode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in theauto-negotiation mode 17.1310FDX1, RO10M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit.If this bit is 1, it means the operation 1 mode is a 10M Full Duplexmode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in theauto-negotiation mode 17.1210HDX1, RO10M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit.If this bit is 1, it means the operation 1 mode is a 10M half duplexmode. The software can read bit[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in theauto-negotiation mode 17.11-RESERVED0, ROReserved 17.9Write as 0, ignore on read17.8-17.4PHYADR[4:0](PHYADR),PHY Address Bit 4:0 RWThe first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiplePHY entities must know the appropriate address of each PHY 17.3-17.0ANMB[3:0]0, ROAuto-negotiation Monitor Bits These bits are for debug only. The auto-negotiation status will bewritten to these bits Final Version: DM9000-DS-F02June 26, 2002 29 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY B3b2b1b0000000010010001101000101011001111000 In IDLE StateAbilityMatch Acknowledge MatchAcknowledge Match FailConsistency MatchConsistency Match Fail Parallel Detects Signal_ link_ readyParallel Detects Signal_ link_ ready FailAuto-negotiation Completed Successfully 8.10 10BASE-T Configuration/Status (10BTCSR) - 18 BitBit NameDefaultDescription18.15RESERVED0, ROReserved Write as 0, ignore on read 18.14LP_EN1, RWLink Pulse Enable 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forcedThis bit is valid only in 10Mbps operation 18.13HBE1,RWHeartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the PHY is configured for full duplex operation, this bit will beignored (the collision/heartbeat function is invalid in full duplexmode) 18.12SQUELCH1, RWSquelch Enable 1 = normal squelch0 = low squelch 18.11JABEN1, RWJabber Enable Enables or disables the Jabber function when the PHY is in10BASE-T full duplex or 10BASE-T transceiver loopback mode1 = Jabber function enabled0 = Jabber function disabled 18.10-RESERVED0, ROReserved 18.1Write as 0, ignore on read18.0POLR0, ROPolarity reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity isreversed. This bit is set and cleared by 10BASE-T moduleautomatically 30 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9. Functional Description 9.1 Host Interface The host interface is the ISA BUS compatible mode.There are eight IO bases, which are 300H, 310H,320H, 330H, 340H, 350H, 360H, and 370H. The IObase is latched from strap pins or loaded from theEEPROM. There are only two addressing ports through theaccess of the host interface. One port is the INDEXport and the other is the DATA port. The INDEX port isdecoded by the pin CMD =0 and the DATA port by thepin CMD =1. The contents of the INDEX port are theregister address of the DATA port. Before the accessof any register, the address of the register must besaved in the INDEX port. location 0x0C00 if the end of address (i.e. 16K) isreached. 9.3 Packet Transmission There are two packets, sequentially named as index Iand index II, can be stored in the TX SRAM at thesame time. The TX Control Register (02h) controls theinsertion of CRC and pads. Their statuses arerecorded at TX Status Register I (03h) and TX StatusRegister II (04h) respectively. The start address of transmission is 00h and thecurrent packet is index I after software or hardwarereset. Firstly write data to the TX SRAM using theDMA port and then write the byte count to byte_ countregister at TX Packet Length Register (0fch/0fdh). Setthe bit 0 of TX Control Register (02h). The DM9000starts to transmit the index I packet. Before thetransmission of the index I packet ends, the data ofthe next (index II) packet can be moved to TX SRAM.After the index I packet ends the transmission, writethe byte count data of the index II to BYTE_COUNTregister and then set the bit 0 of TX Control Register(02h) to transmit the index II packet. The followingpackets, named index I, II, I, II,…, use the same wayto be transmitted.9.4 Packet Reception The RX SRAM is a ring data structure. The startaddress of RX SRAM is 0C00h after software orhardware reset. Each packet has a 4-byte headerfollowed with the data of the reception packet whichCRC field is included. The format of the 4-byte headeris 01h, status, BYTE_COUNT low, and BYTE_COUNT high. It is noted that the start addressof each packet is in the proper address boundarywhich depends on the operation mode (the 8-bit, 16-bit or 32-bit mode ). 9.2 Direct Memory Access Control The DM9000 provides DMA capability to simplify theaccess of the internal memory. After the programmingof the starting address of the internal memory andthen issuing a dummy read/write command to load thecurrent data to internal data buffer, the desiredlocation of the internal memory can be accessed bythe read/write command registers. The memory’saddress will be increased with the size that equals tothe current operation mode (i.e. the 8-bit, 16-bit or 32-bit mode) and the data of the next location will beloaded into internal data buffer automatically. It isnoted that the data of the first access (the dummyread/write command) in a sequential burst should beignored because that the data was the contents of thelast read/write command. The internal memory size is 16K bytes. The firstlocation of 3K bytes is used for the data buffer of thepacket transmission. The other 13K bytes are used forthe buffer of the receiving packets. So in the writememory operation, when the bit 7 of IMR is set, thememory address increment will wrap to location 0 ifthe end of address (i.e. 3K) is reached. In a similarway, in the read memory operation, when the bit 7 ofIMR is set, the memory address increment will wrap to Final Version: DM9000-DS-F02June 26, 2002 31 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9.5 100Base-TX Operation The block diagram in figure 3 provides an overview ofthe functional blocks contained in the transmit section.The transmitter section contains the followingfunctional blocks: - 4B5B Encoder- Scrambler - Parallel to Serial Converter- NRZ to NRZI Converter- NRZI to MLT-3- MLT-3 Driver9.5.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble datagenerated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, see referenceTable 1. This conversion is required for control andpacket data to be combined in code groups. The4B5B encoder substitutes the first 8 bits of the MACpreamble with a J/K code-group pair (11000 10001)upon transmit. The 4B5B encoder continues toreplace subsequent 4B preamble and data nibbleswith corresponding 5B code-groups. At the end of thetransmit packet, upon the deassertion of the TransmitEnable signal from the MAC Reconciliation layer, the4B5B encoder injects the T/R code-group pair (0110100111) indicating the end of frame. After the T/Rcode-group pair, the 4B5B encoder continuouslyinjects IDLEs into the transmit data stream untilTransmit Enable is asserted and the next transmitpacket is detected. The DM9000 includes a Bypass 4B5B conversionoption within the 100Base-TX Transmitter for supportof applications like 100 Mbps repeaters which do notrequire 4B5B conversion. 9.5.2 Scrambler The scrambler is required to control the radiatedemissions (EMI) by spreading the transmit energyacross the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation. By scrambling the data, the total energy presented tothe cable is randomly distributed over a widefrequency range. Without the scrambler, energy levelson the cable could peak beyond FCC limitations atfrequencies related to the repeated 5B sequences,like the continuous transmission of IDLE symbols. Thescrambler output is combined with the NRZ 5B datafrom the code-group encoder via an XOR logicfunction. The result is a scrambled data stream withsufficient randomization to decrease radiatedemissions at critical frequencies.9.5.3 Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5Bscrambled data from the scrambler, and serializes it(converts it from a parallel to a serial data stream).The serialized data stream is then presented to theNRZ to NRZI encoder block9.5.4 NRZ to NRZI Encoder After the transmit data stream has been scrambledand serialized, the data must be NRZI encoded forcompatibility with the TP-PMD standard, for 100Base-TX transmission over Category-5 unshielded twistedpair cable. 9.5.5 MLT-3 Converter The MLT-3 conversion is accomplished by convertingthe data stream output, from the NRZI encoder intotwo binary data streams, with alternately phased logicone event.9.5.6 MLT-3 Driver The two binary data streams created at the MLT-3converter are fed to the twisted pair output driver,which converts these streams to current sources andalternately drives either side of the transmittransformer’s primary winding, resulting in a minimalcurrent MLT-3 signal. Refer to figure 4 for the blockdiagram of the MLT-3 converter. 32 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9.5.7 4B5B Code Group Symbol01234567ABCDEFIJKTRHVVVVVVVVVV MeaningData 0Data 1Data 2Data 3Data 4Data 5Data 6Data 7Data 8Data 9Data AData BData CData DData EData FIdleSFD (1)SFD (2)ESD (1)ESD (2)ErrorInvalidInvalidInvalidInvalidInvalidInvalidInvalidInvalidInvalidInvalid 4B code32100000000100100011010001010110011110001001101010111100110111101111undefined01010101undefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedundefinedTable 1 5B Code432101111001001101001010101010010110111001111100101001110110101111101011011111001110111111110001000101101001110010000000000010001000011001010011001000011001000011001 Final Version: DM9000-DS-F02June 26, 2002 33 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9.6 100Base-TX Receiver The 100Base-TX receiver contains several functionblocks that convert the scrambled 125Mb/s serial datato synchronous 4-bit nibble data that is then providedto the MII. The receive section contains the following functionalblocks: - Signal Detect - Digital Adaptive Equalization- MLT-3 to Binary Decoder- Clock Recovery Module- NRZI to NRZ Decoder- Serial to Parallel- Descrambler - Code Group Alignment- 4B5B Decoder9.6.1 Signal Detect The signal detect function meets the specificationsmandated by the ANSI XT12 TP-PMD 100Base-TXstandards for both voltage thresholds and timingparameters. 9.6.2 Adaptive Equalization When transmitting data over copper twisted pair cableat high speed, attenuation based on frequencybecomes a concern. In high speed twisted pairsignaling, the frequency content of the transmittedsignal can vary greatly during normal operation basedon the randomness of the scrambled data stream.This variation in signal attenuation, caused byfrequency variations, must be compensated for toensure the integrity of the received data. In order toensure quality transmission when employing MLT-3encoding, the compensation must be able to adapt tovarious cable lengths and cable types depending onthe installed environment. The selection of long cablelengths for a given implementation requires significantcompensation, which will be over-killed in a situationthat includes shorter, less attenuating cable lengths.Conversely, the selection of short or intermediatecable lengths requiring less compensation will causeserious under-compensation for longer length cables.Therefore, the compensation or equalization must beadaptive to ensure proper conditioning of the received signal independent of the cable length.9.6.3 MLT-3 to NRZI Decoder The DM9000 decodes the MLT-3 information from theDigital Adaptive Equalizer into NRZI data. Therelationship between NRZI and MLT-3 data is shownin figure 4. 9.6.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data fromthe MLT-3 to NRZI decoder. The Clock RecoveryModule locks onto the data stream and extracts the125Mhz reference clock. The extracted andsynchronized clock and data are presented to theNRZI to NRZ decoder. 9.6.5 NRZI to NRZ The transmit data stream is required to be NRZIencoded for compatibility with the TP-PMD standardfor 100Base-TX transmission over Category-5unshielded twisted pair cable. This conversionprocess must be reversed on the receive end. TheNRZI to NRZ decoder, receives the NRZI data streamfrom the Clock Recovery Module and converts it to aNRZ data stream to be presented to the Serial toParallel conversion block.9.6.6 Serial to Parallel The Serial to Parallel Converter receives a serialdata stream from the NRZI to NRZ converter. Itconverts the data stream to parallel data to bepresented to the descrambler. 9.6.7 Descrambler Because of the scrambling process requires to controlthe radiated emissions of transmit data streams, thereceiver must descramble the receive data streams.The descrambler receives scrambled parallel datastreams from the Serial to Parallel converter, and itdescrambles the data streams, and presents the datastreams to the Code Group alignment block. 34 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC controller with integrated 10/100 PHY 9.6.8 Code Group Alignment The Code Group Alignment block receives un-aligned5B data from the descrambler and converts it into 5Bcode group data. Code Group Alignment occurs afterthe J/K is detected, and subsequent data is aligned ona fixed boundary.9.6.9 4B5B Decoder The 4B5B Decoder functions as a look-up table thattranslates incoming 5B code groups into 4B (Nibble)data. When receiving a frame, the first 2 5-bit codegroups receive the start-of-frame delimiter (J/Ksymbols). The J/K symbol pair is stripped and twonibbles of preamble pattern are substituted. The lasttwo code groups are the end-of-frame delimiter (T/RSymbols). The T/R symbol pair is also stripped from the nibble,presented to the Reconciliation layer.9.7 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant.When the DM9000 is operating in 10Base-T mode,the coding scheme is Manchester. Data processed fortransmit is presented to the MII interface in nibbleformat, converted to a serial bit stream, then theManchester encoded. When receiving, the bit stream,encoded by the Manchester, is decoded andconverted into nibble format to present to the MIIinterface. 9.8 Collision Detection For half-duplex operation, a collision is detected whenthe transmit and receive channels are activesimultaneously. When a collision is detected, it will bereported by the COL signal on the MII interface. Collision detection is disabled in Full Duplexoperation.9.9 Carrier Sense Carrier Sense (CRS) is asserted in half-duplexoperation during transmission or reception of data.During full-duplex mode, CRS is asserted only duringreceive operations.9.10 Auto-Negotiation The objective of Auto-negotiation is to provide ameans to exchange information between linkeddevices and to automatically configure both devices totake maximum advantage of their abilities. It isimportant to note that Auto-negotiation does not testthe characteristics of the linked segment. The Auto-Negotiation function provides a means for a device toadvertise supported modes of operation to a remotelink partner, acknowledge the receipt andunderstanding of common modes of operation, and toreject un-shared modes of operation. This allowsdevices on both ends of a segment to establish a linkat the best common mode of operation. If more thanone common mode exists between the two devices, amechanism is provided to allow the devices to resolveto a single mode of operation using a predeterminedpriority resolution function. Auto-negotiation also provides a parallel detectionfunction for devices that do not support the Auto-negotiation feature. During Parallel detection there isno exchange of information of configuration. Instead,the receive signal is examined. If it is discovered thatthe signal matches a technology, which the receivingdevice supports, a connection will be automaticallyestablished using that technology. This allows devicesnot to support Auto-negotiation but support a commonmode of operation to establish a link. Final Version: DM9000-DS-F01April 12, 2002 35 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 9.11 Power Reduced Mode The Signal detect circuit is always turned to monitor whetherthere is any signal on the media (cable disconnected). TheDM9000 automatically turns off the power and enters thePower Reduced mode, whether its operation mode is N-way or force mode. When enters the Power Reducedmode, the transmit circuit still sends out fast link pules withminimum power consumption. If a valid signal is detectedfrom the media, which might be N-ways fast link pules,10Base-T normal link pules, or 100Base-TX MLT3 signals,the device will wake up and resume a normaloperation mode. That can be writing Zero to Reg.16.4 of MII register todisable Power Reduced mode. 9.11.1 Power Down Mode The Reg.0.11 of MII register can be set high to enter thePower Down mode, which disables all transmit, receivefunctions and MII interface functions, except the MDC/MDIOmanagement interface. 9.11.2 Reduced Transmit Power Mode The additional Transmit power reduction can begained by designing with 1.25:1 turns ration magneticon its TX side and using a 8.5KΩ resistor on BGRESand AGND pins, and the TXO+/TXO- pulled highresistors should be changed from 50Ω to 78Ω.This configuration could be reduced about 20%transmit power. 36 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10. DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings ( 25°C ) SymbolParameterDVDD AVDDSupply Voltage VINDC Input Voltage (VIN)VOUTDC Output Voltage(VOUT)TstgStorage Temperature Rang (Tstg)TcCase TemperatureLTLead Temp. (TL, Soldering, 10 sec.)ESDESD rating (Rzap=1.5k Czap=100PF) Min. -0.3-0.5-0.3-650---Max.3.65.53.6+150852353000 UnitVVV°C°C°CV Conditions EIAJ-4701Air Flow = 0m/minJ-STD-020AHuman Body Mode 10.2 Operating Conditions SymbolParameterDVDD,AVDDSupply Voltage PD100BASE-TX (Power Dissipation)10BASE-T TX 10BASE-T idleAuto-negotiation Power Reduced Mode(without cable)Power Down Mode Min.3.135------------------Max.3.4651008544602010UnitVmAmAmAmAmAmA Conditions 3.3V3.3V3.3V3.3V3.3V3.3V Comments Stresses above, which are listed under “AbsoluteMaximum Ratings”, may cause permanent damage tothe device. These are stress ratings only. Functionaloperation of this device at these or any otherconditions above, which indicated in the operational sections of this specification, is not implied. Exposureto absolute maximum rating conditions for extendedperiods may affect the reliability of the device. Final Version: DM9000-DS-F02June 26, 2002 37 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10.3 DC Electrical Characteristics (VDD = 3.3V)SymbolParameterInputs VILInput Low VoltageVIHInput High VoltageIILInput Low Leakage CurrentIIHInput High Leakage CurrentOutputsVOLOutput Low VoltageVOHOutput High VoltageReceiverVICMRX+/RX- Common Mode Input Voltage Transmitter VTD100100TX+/- Differential Output Voltage VTD1010TX+/- Differential Output VoltageITD100100TX+/- Differential Output Current ITD1010TX+/- Differential Output Current Min.-2.0 -1--2.4-Typ.------0.9 Max.0.8--10.4--UnitVVuAuAVVV Conditions VIN = 0.0VVIN = 3.3VIOL = 4mAIOH = -4mA100 Ω TerminationAcross Peak to PeakPeak to PeakAbsolute ValueAbsolute Value 1.94.4│19││44│ 2.05│20││50│ 2.15.6│21││56│ VVmAmA 38 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10.4 AC Electrical Characteristics & Timing Waveforms10.4.1 TP InterfaceSymbolParametertTR/F100TX+/- Differential Rise/Fall TimetTM100TX+/- Differential Rise/Fall Time Mismatch tTDC100TX+/- Differential Output Duty Cycle Distortion tT/T100TX+/- Differential Output Peak-to-Peak Jitter XOST100TX+/- Differential Voltage Overshoot10.4.2 Oscillator/Crystal TimingSymbolParametertCKCTCKCtPWHTCKCtPWLOSC Pulse Width Low10.4.3 Processor Register Read Timing Min. 3.00000 Typ.----- Max.5.00.50.51.45 Unitnsnsnsns% Conditions Min.39.9981616Typ.402020Max.40.0022424Unitnsnsns Conditions50ppm AEN,SA,CMDIOR→T1←→T5←←SDT2T3←→→←T4T6→←IO16,IO32→Note 1.2→←T7→←T8SymbolT1T2T3T4T5T6T7T8Parameter System address valid to IOR validIOR width SD Setup time IOR invalid to SD invalid IOR invalid to system address invalid IOR invalid to next IOR valid （access DM9000）System address valid to IO16,IO32 validSystem address invalid to IO16, IO32 invalid Min.522 Typ.Max. 104 580 55 Unitnsnsnsnsnsnsnsns 39 Final Version: DM9000-DS-F02June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY Note： 1. The IO16 is valid when the SD bus width is 16-bit or32-bit, and the system address is data port (i.e.CMD is high) and the value of address port ismemory data register index.（ex. F0H, F2H, F6H orF8H） 2. The IO32 is valid when the SD bus width is 32-bit,the system address is data port (i.e. CMD is high)and the value of address port is memory data register index（ex. F0H, F2H, F6H or F8H） 10.4.4 Processor Register Write Timing →AEN,SA,CMDIOWSDIO16,IO32T1←→T2←T5←←T6→→ ∫∫→←T4T3←→←T7→→←T8Note1.2SymbolT1T2T3T4T5T6T7T8Parameter System Address Valid to IOW ValidIOW WidthSD Setup TimeSD Hold Time IOW Invalid to System Address Invalid IOW Invalid to Next IOW validaccess DM9000）System Address Valid to IO16, IO32 ValidSystem Address Invalid to IO16, IO32 Invalid Min.522225584 Typ.Max. 55 Unitnsnsnsnsnsnsnsns Note： 1. The IO16 is valid when the SD bus width is 16-bit or32-bit and system address is data port (i.e. CMD ishigh) and the value of address port is memory dataregister index (ex. F0H, F2H, F6H or F8H） 2. The IO32 is valid when the SD bus width is 32-bitand system address is data port (i.e. CMD is high)and the value of address port is memory data register index (ex. F0H, F2H, F6H or F8H) 40 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10.4.5 External MII Interface Transmit Timing T2←TXCKTXEN ∫∫→∫∫→TXD[3:0]T1←∫∫SymbolT1T2Parameter TXEN,TXD[3：0] Setup TimeTXEN,TXD[3：0] Hold Time Min. Typ.328 Max. Unitnsns 10.4.6 External MII Interface Receive Timing RXCKRXER,RXDV∫∫→RXD[3:0]T1←∫∫→T2←SymbolT1T2Parameter RXER, RXDV,RXD[3：0] Setup TimeRXER, RXDV,RXD[3：0] Hold TimeMin.55 Typ. Max.Unit nsns Final Version: DM9000-DS-F02June 26, 2002 41 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 10.4.7 MII Management Interface Timing ←MDCT1→→T2MDIO (drive by DM9601)MDIO (drive by externcl MII)←→←T3→ →←UnitMhznsnsnsns ←T5T4SymbolT1T2T3T4T5 Parameter MDC Frequency MDIO by DM9000 Setup TimeMDIO by DM9000 Hold Time MDIO by External MII Setup TimeMDIO by External MII Hold Time Min. Typ.2187313 Max. 4040 10.4.8 EEPROM Interface Timing →EESSEECKEEDOEEDI←T2→→T4T1←←→←T5∫∫→T6←T7→SymbolT1T2T3T4T5T6T7 42 ←UnitMhznsnsnsnsnsns Final Version: DM9000-DS-F02 June 26, 2002 Parameter EECK FrequencyEECS Setup TimeEECS Hold TimeEEDO Setup TimeEEDO Hold TimeEEDI Setup TimeEEDI Hold Time Min. Typ.0.375500216802200 Max. 8080 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY Final Version: DM9000-DS-F02June 26, 2002 43 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11. Application Notes 11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45connector. Place all the 50Ω resistors as close aspossible to the DM9000 RXI± and TXO± pins. Tracesrouted from RXI± and TXO± to the transformer should runin close pairs directly to the transformer. The designershould be careful not to cross the transmit and receive pairs.As always, vias should be avoided as much as possible.The network interface should be void of any signals otherthan the TXO± and RXI± pairs between the RJ-45 to thetransformer and the transformer to the DM9000.. Thereshould be no power or ground planes in the area under the11.2 10Base-T/100Base-TX Application network side of the transformer to include the area under theRJ-45 connector. (Refer to Figure 4 and 5) Keep chassisground away from all active signals. The RJ-45 connectorand any unused pins should be tied to chassis groundthrough a resistor divider network and a 2KV bypasscapacitor. The Band Gap resistor should be placed as physically closeas pins 25 and 26 as possible (refer to Figure 1 and 2).The designer should not run any high-speed signal near theBand Gap resistor placement. RXI+2950Ω1%300.1µF50ΩAGND1%3.3V AVDD0.1µF0.1µFAGNDAGNDTransformer1:1361451:12780.1µF75Ω1%75Ω1%75Ω1%RJ45 RXI-DM9000 TX0+50Ω1%3350Ω1%3.3V AVCC TX0-34BGRESBGGND26AGND256.8KΩ, 1%75Ω1%0.1µF/2KVAGNDChasis GNDFigure 11-1 44 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.3 10Base-T/100Base-TX (Power Reduction Application) RXI+2950Ω1%3050ΩAGND1%3.3V AVDD0.1µFTransformer1:13610.1µFRJ45RXI-4AGNDDM9000TX+78Ω1%AGND3378Ω1%340.1µF51.25:12783.3V AVCCTX0-0.1µFBGRESBGGND2625AGND8.5KΩ, 1%75Ω1%75Ω1%75Ω1%75Ω1%0.1µF/2KV or 0.01µF/2KVAGNDChasis GNDFigure 11-2 Final Version: DM9000-DS-F02June 26, 2002 45 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.4 Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close aspossible to the power pads of the DM9000 (The best placeddistance is < 3mm from pin). The recommended decoupling capacitor is 0.1μF or 0.01μF, as required bythe design layout. 9057372DM9000205527283536Figure 11-3 46 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.5 Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI. Ground plane partitioningcan cause increased EMI emissions that could make the network interface card not comply with specific FCCregulations (part 15). Figure 4 shows a recommendedground layout scheme. Figure 11-4 Final Version: DM9000-DS-F02June 26, 2002 47 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.6 Power Plane Partitioning The power planes should be approximately illustrated inFigure 5. The ferrite bead used should perform an impedance at least 75Ω at 100MHz. A suitable bead isthe Panasonic surface mound bead, part number EXCCL4532U or equivalent. A 10μF electrolytic bypasscapacitors should be connected between VDD and Groundat the device side of each of the ferrite bead. Figure 11-5 48 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.7 Magnetics Selection Guide Refer to Table 2 for transformer requirements.Transformers, meeting these requirements, areavailable from a variety of magnetic manufacturers.Designers should test and qualify all magnetics beforeManufacturer Pulse EngineeringDeltaYCLHalo using them in an application. The transformers listedin Table 2 are electrical equivalents, but may not bepin-to-pin equivalents. Nano Pulse Inc.Fil-MagBel FuseValor Macronics Part Number PE-68515, H1078, H1012H1102 LF8200, LF8221x20PMT04, 20PMT05 TG22-3506ND, TD22-3506G1, TG22-S010ND TG22-S012ND NPI 6181-37, NPI 6120-30, NPI 6120-37NPI 6170-30PT41715 S558-5999-01ST6114, ST6118HS2123, HS2213Table 2 11.8 Crystal Selection Guide A crystal can be used to generate the 25MHzreference clock instead of a oscillator. The crystalmust be a fundamental type, and series-resonant. Connects to X1_25M and X2_25M, and shunts eachcrystal lead to ground with a 22pf capacitor (see figure6). X2_25M2122X1_25MY1C1822pfAGND25MC1922pfAGNDFigure 11-6 Crystal Circuit Diagram Final Version: DM9000-DS-F02June 26, 2002 49 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 11.9 Application of reverse MII RXCLKTXCLKRXD0RXD1RXD2RXD3TXD0TXD1TXD2TXD3RXDVTXENCRSCOLRXERMDCMDIO TXCLKRXCLKTXD0TXD1TXD2TXD3RXD0RXD1RXD2RXD3TXENRXDVCRSCOLRXERTXERMDCMDIO DM9000 SWITCHHUB Reverse MII Link Full Mode (Reverse MII Figure 11-7 Normal MIINormal MII) Note: When operating DM9000 at Reverse MII mode, pin 87 is pulled high . At this application, the txclk , col and crs pins will be changed from input to output. 50 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 12. Package Information 12.1 LQFP 100L Outline Dimensions HD75 Unit: Inches/mm 51D7650100F26125EHEeGDbcGD~~A2See Detail FSeating PlaneA1AyDLL1Detail FSymbolAA1A2bcDEeFGDHDHELL1yθDimensions In Inches0.063 Max.0.004 ± 0.0020.055 ± 0.0020.009± 0.0020.006± 0.0020.551 ± 0.0050.551 ± 0.0050.020 BSC.0.481 NOM.0.606 NOM.0.630 ± 0.0060.630 ± 0.0060.024 ± 0.0060.039 Ref.0.004 Max.0° ~ 12°Dimensions In mm1.60 Max.0.1 ± 0.051.40 ± 0.050.22± 0.050.15± 0.0514.00 ± 0.1314.00 ± 0.130.50 BSC.12.22 NOM.15.40 NOM.16.00 ± 0.1516.00 ± 0.150.60 ± 0.151.00 Ref.0.1 Max.0° ~ 12°Notes: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only.3. All dimensions are based on metric system. Final Version: DM9000-DS-F02June 26, 2002 51 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 13. APPENDIX: 1. Data Sheet Changed Errata List Items123456Before Modification 4BKPM 3 BKPA Data & Ver. 05/02/2001 P0106/14/2001 P0106/22/2001 P0112/05/2001 P0212/05/2001 P0212/05/2001 P02 PagePage 1Page 14Page 7Page 11Page 38 Content DM9000 Data Sheet StartModify Block DiagramCheck TableA-1-A &A-1-BCheck TableA-2-A &A-2-BCheck TableA-3-A &A-2-BCheck TableA-4-A &A-4-B 0,RW0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when a packet’s DA match and RX SRAM over BPHW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when any packet coming and RX SRAM over BPHW Table A-1-A After Modification 4BKPA 3 BKPM 0,RW0,RW Back pressure mode. This mode is for half duplex mode only. Generate a jam pattern when any packet coming and RX SRAM over BPHW Back pressure mode. This mode is for half duplex mode only. Generate a jampattern when a packet’s DA match and RX SRAM over BPHW Table A-1-B Before Modification 16,17,18,TEST1~TEST4 19 I Operation Mode Test1,2,3,4=(1,1,0,0) : the processor interface is ISA compatible Test1,2,3,4=(1,1,0,1) : the processor interface is for general processor Table A-2-A After Modification 16,17,18,TEST1~TEST4 19 I Operation Mode Test1,2,3,4=(1,1,0,0) in normal application Table A-2-B Before ModificationBitName2:1LBK Default 00,RW Description Loopback modeBit 2 1 0 0 normal 0 1 MAC internal loopback 1 0 internal PHY digital loopback 1 1 internal PHY analog loopback Table A-3-A 52 Final Version: DM9000-DS-F02 June 26, 2002 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY After ModificationBitName2:1LBK Default 00,RW Description Loopback modeBit 2 1 0 0 normal 0 1 MAC internal loopback 1 0 internal PHY 100M mode digital loopback 1 1 (Reserved) Table A-3-B Before ModificationSymbolParameterT3SD Setup time IOW invalid to next IOW （access DM9000）T6 TableA-4-A Min. 580 Typ.Max. Unitnsns After ModificationSymbolParameterT3SD Setup time IOW invalid to next IOW （access DM9000）T6 Table A-4-B Min. 2284 Typ.Max. Unitnsns Final Version: DM9000-DS-F02June 26, 2002 53 DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY 14. Order Information Part NumberDM9000E Pin Count 100 PackageLQFP DAVICOM‘s terms and conditions printed on the orderacknowledgment govern all sales by DAVICOM.DAVICOM will not be bound by any terms inconsistentwith these unless DAVICOM agrees otherwise inwriting. Acceptance of the buyer’s orders shall bebased on these terms. Disclaimer The information appearing in this publication isbelieved to be accurate. Integrated circuits sold byDAVICOM Semiconductor are covered by thewarranty and patent indemnification, and theprovisions stipulated in the terms of sale only.DAVICOM makes no warranty, express, statutory,implied or by description, regarding the information inthis publication or regarding the freedom of thedescribed chip(s) from patent infringement.FURTHER, DAVICOM MAKES NO WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANYPURPOSE. DAVICOM reserves the right to haltproduction or alter the specifications and prices at anytime without notice. Accordingly, the reader iscautioned to verify that the data sheets and otherinformation in this publication are current beforeplacing orders. Products described herein areintended for use in normal commercial applications.Applications involving unusual environmental orreliability requirements, e.g. military equipment ormedical life support equipment, are specifically notrecommended without additional processing byDAVICOM for such applications. Please note thatapplication circuits illustrated in this document are forreference purposes only. Company Overview DAVICOM Semiconductor Inc. develops and manufactures integrated circuits for integration intodata communication products. Our mission is to design and produce IC products that are the industry’sbest value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, wehave built an organization that is able to developchipsets in response to the evolving technologyrequirements of our customers while still deliveringproducts that meet their cost requirements. Products We offer only products that satisfy highperformance requirements and which are compatible with major hardware and softwarestandards. Our currently available and soon tobe released products are based on our proprietarydesigns and deliver high quality, high performance chipsets that comply with modemcommunication standards and Ethernetnetworking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at:HeadquartersHsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX,Science-based Park, Hsin-chu City, Taiwan, R.O.C.TEL: 886-3-5798797FAX: 886-3-5798858 Sales & Marketing Office:2F, No. 5, Industry E. Rd., IX,Hsin-chu City, Taiwan, R.O.C.TEL: 886-3-5798797FAX: 886-3-56929 Email: sales@davicom.com.twWeb site: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at nearthe limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. 54 Final Version: DM9000-DS-F02 June 26, 2002 This datasheet has been downloaded from: www.EEworld.com.cn Free Download Daily Updated Database 100% Free Datasheet Search Site 100% Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www.EEworld.com.cn All Datasheets Cannot Be Modified Without Permission Copyright © Each Manufacturing Company
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